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7.1: Introduction

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    Decoders are circuits which break an n-bit input into 2n individual output lines. For example, a decoder could break down 2 bit operations code into 4 separate operations. The operation code tells the CPU which operations to run. A 2 bit operation code is summarized in the following table. Here the code 00 corresponds to the operation ADD, 01 corresponds, to SUB, etc.

    Figure \(\PageIndex{1}\): Control lines for ALU

    Code

    Operation

    00

    ADD

    01

    SUB

    10

    MUL

    11

    DIV

    The Control Unit (CU) of the CPU would break the binary number down so that each operation would match exactly one control line. This is called a 2-to-4 decoder since 2 input bits are converted into 4 output lines. A schematic of the decoder to implement this CU is shown in the figure below.

    Figure \(\PageIndex{2}\): Decoder used to set ALU control lines

    Screen Shot 2020-06-26 at 7.40.25 PM.png

    Most CPUs support instruction sets that are much larger than simply ADD/SUB/MUL/DIV, and thus a 2-to-4 decoder is not that common, however the principals used to create a 2-to-4 decoder are the same even as the size of the decoder becomes larger. This chapter will only look at the 2-to-4 decoder. Larger decoders will be considered in the exercises at the end of the chapter.


    This page titled 7.1: Introduction is shared under a CC BY 4.0 license and was authored, remixed, and/or curated by Charles W. Kann III via source content that was edited to the style and standards of the LibreTexts platform.