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9.3: Latches

  • Page ID
    27004
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    A latch is a way to implement a circuit which maintains a data value of high (1) or low (0) so long as current is maintained in the circuit. Latches implement static memory that is used to maintain the state of the CPU.

    \(\PageIndex{1}\) D Latch

    There are many types of latches, including the R-S latch, T latch, and D latch. The only latch needed in this text is the D latch, shown in Figure \(\PageIndex{1}\), so it will be the only one covered. A D latch is a circuit that is set using an input value named D and a clock pulse. When the clock pulse is high (or 1), the value of the D latch changes to the input value of D. When the clock cycle is low (or 0) the value of the latch will maintain the last D value it received when a clock cycle was high. The value which is saved in the D latch is named Q, and both Q and its complement Q' are output from the circuit.

    Figure \(\PageIndex{1}\): D latch

    Screen Shot 2020-06-26 at 10.06.09 PM.png

    The truth-table in Figure \(\PageIndex{2}\) gives the characteristics of the D latch. While the value of clock is 0, the D latch does not change value, and thus Qnew = Qcurrent. When the clock is 1, the D latch is set to the input value of D, and Qnew takes on the value of D.

    Figure \(\PageIndex{2}\): Characteristic truth-table for a D latch

    Input

    Output

    D

    Clock Qnew Comment
    x 0

    Qcurrent

    State does not change

    0 1 0  
    1 1 1  

    To create multi-byte memory cells, multiple D latches are combined.

    While the version of the D latch described above is sufficient for storing data values, to be useful in a CPU the D latch needs to have an addition input called an enable bit. The enable bit allows the D latch to be set in only specific situations, not simply every time the clock is high. The D latch with an enable bit is shown in the Figure \(\PageIndex{3}\).

    Figure \(\PageIndex{3}\): D latch with enable bit

    Screen Shot 2020-06-26 at 10.13.36 PM.png

    The truth-table which characterizes this D latch is shown in Figure \(\PageIndex{4}\). The implementation of this version D latch is left as an exercise at the end of the chapter. Note that an X in a column is a don't care condition, e.g. it does not matter what value is used as this input is not used.

    Figure \(\PageIndex{4}\): Truth-table for a D latch with enable bit

    Input

    Output

    D

    Enable

    Clock

    Qnew

    Comment

    x

    X

    0

    Qcurrent

    State does not change

    x

    0

    X

    Qcurrent

    State does not change

    0 1 1 0  
    1 1 1 1  

    \(\PageIndex{2}\) Circuit diagram for a D latch

    The circuit diagram for a D latch is shown in Figure \(\PageIndex{5}\). This latch circuit will be explained in two steps. The first step will explain why the latch maintains its current state (Qnew = Qcurrent) if the clock is low. The second step will explain why the latch changes state (Qnew = D) if the clock is high.

    In the first step, note that the lines InputA and InputB must always be high (1) if the Clock input is low (0). Therefore the area which is circled in the diagram below can be analyzed without considering any other part of the circuit.

    Figure \(\PageIndex{5}\): Circuit diagram for a D latch

    Screen Shot 2020-06-26 at 10.20.56 PM.png

    Remember that a NAND of 1 with any value (e.g. Q) is simply its complement (e.g. Q'). So once the circuit is set, so that the outputs are Q and Q', it is easy to see that the output of the top NAND gate is Q (e.g. (Q'*1)' = Q), and the output of the bottom NAND gate is Q' (e.g. (Q*1)' = Q'). Thus if Q and Q' are loaded into the circuit and the clock is 0, the circuit will maintain the values of Q and Q', and the latch keeps its current value.

    Next the question is if the Clock line becomes high (1), how does it force the value of D into the latch. To see this, note that if the Clock become 1, the InputA = D' and InputB = D must be true. Thus one of the lines must be 0. Again consider the part of the circuit which has been circled. The line which is 0 will force its output to be 1 (e.g. if Input-A = 1, Q = 1, or if Input-B = 0, Q' = 1). This will eventually force the output of the other NAND gate to 0, though it might take some time to settle to this value. So long as the time needed for the circuit to settle is less than the clock speed (the length of the clock pulse), the circuit will become stable with Q = D and Q'=D'. So the result of the clock being high is that the latch will store in its state the value of Q = D and Q' = D'.

    Before the first clock pulse, the state of the latch is simply invalid, and the value of the latch cannot be used until after it is set with the first clock pulse.

    \(\PageIndex{3}\) Implementing the D latch

    Implementing the D latch will require 2 switches, one NOT gate (7404 chip) and 4 NAND gates (7400 chip), and 2 LEDs for Q and Q'. In this lab a clock is not used, and instead is simulated by the second switch. Also in this diagram the two lines running from the output of the NAND gates backwards to the input of the other NAND gate use green wire.

    Figure \(\PageIndex{6}\): Implementation of a D latch

    Screen Shot 2020-06-26 at 10.22.52 PM.png

    The following steps describe the implementation of the D latch, and correspond to the circuit in Figure \(\PageIndex{6}\).

    1. Install and power two switches (D and Clock), and the two output LEDs (Q and Q').
    2. Install and power the 7404 (NOT gate) chip.
    3. Install and power the 7400 (NAND gate) chip.
    4. Connect the D switch to the first NOT gate (pin 1 on the 7404 chip). The output from this NOT gate, D’, is on pin 2.
    5. Connect the CLK switch and the D' output (pin 2 and on the 7404 chip) to the first NAND gate, pins 1 and 2 on the 7400 chip. The output from this NAND gate will be on pin 3 of the 7400 chip, and used in step 5 (pin 3 on the 7400 chip).
    6. Connect the output from step 4 (pin 3 on the 7400 chip) to the second NAND gate (pin 4 on the 7400 chip). Connect the output from step 7 (pin 8 on the 7400 chip) to the second input (pin 5 on the 7400 chip). The output from this NAND gate (pin 6 on the 7400 chip) will be sent to Q' and used in step 7 (pin 10 on the 7400 chip).
    7. Connect the D and Clock switches to the third input NAND gate (pins 12 and 13 on the 7400 chip). The output of this NAND gate will be on pin 11 of the 7400 chips, and used in step 7 (pin 9 on the 7400 chip).
    8. Connect the output from steps 5 and 6 (pins 6 and 11 on the 7400 chip) to the inputs of the fourth NAND gate (pins 9 and 10 of the 7400 chip). The output from this NAND gate (pin 8 on the 7400 chip) will be sent to the input of step 4 (pin 4 on the 7400 chip), and to Q'.

    When implemented correctly, the output Q and Q' lights will follow the D switch if the CLK switch is set to 1, or the on position. If the CLK is set to 0, or the off position, the lights will not change.

    Figure \(\PageIndex{7}\): 7475 pin configuration

    Screen Shot 2020-06-26 at 10.25.48 PM.png

    \(\PageIndex{4}\) D latch as a single IC chip

    The D latch is a common IC, and it has been implemented as a single chip, the 7475 chip. The 7475 chip is called 4-bit bistable latch because each chip has four 1-bit D latches. A D latch is bistable because it has 2 stable states, 0 or 1. The circuit implemented here will use only one of the D latches available on the 7475 chip.

    The layout of the 7475 chip is somewhat complex. The pin configuration is given in Figure \(\PageIndex{7}\) and a table for the meaning of each pin in Figure \(\PageIndex{8}\). The implementation of the circuit in this section will only use pins 1, 2, 5, 12, 13 and 16. The other pins will simply be left open, and not discussed further.

    Figure \(\PageIndex{8}\): 7475 pin meanings

    Symbol

    Pin

    Description

    1Q'

    1

    complementary latch output 1

    1D

    2

    data input 1

    2D

    3

    data input 2

    LE34

    4

    latch enable input for latches 3 and 4 (active high)

    Vcc

    5

    positive supply voltage

    3D

    6

    data input 3

    4D

    7

    7 data input 4

    4Q'

    8

    complementary latch output 4

    4Q

    9

    latch output 4

    3Q

    10

    latch output 3

    3Q'

    11

    complementary latch output 3

    GND

    12

    Ground

    LE12

    13

    latch enable input for latches 1 and 2 (active high)

    2Q'

    14

    complementary latch output 2

    2Q

    15

    15 latch output 2

    1Q

    16

    15 latch output 1

    \(\PageIndex{5}\) Implementation of a D latch using a 7475 chip

    Figure \(\PageIndex{9}\) implements the same circuit as in Figure \(\PageIndex{6}\), but now the 7475 chip is used. The following steps outline how to implement this circuit, and the meaning of each connection.

    1. Insert the switches for the inputs CLK and D, and the LEDs for the outputs Q and Q'.
    2. Insert and power the 7475 chip. Note that the power is very different from any other chip that has been used up to this point. The positive and ground wires are on opposite sides of the chip, and they are on pins 5 and 12. Make sure you install the power correctly, and check the chip after powering it to see if it is hot. If it is hot, you have wired it incorrectly.
    3. Connect the D input to pin 2 on the 7475 chip.
    4. Connect the CLK to pin 13 on the 7475 chip. This is labeled LE12, or latch enabled input for latches 1 and 2, enabled high. Enabled high means connected to the positive rail or set to the value of 1, and enabled low means connected to the ground rail or set to the value of 0. So this chip enables latch 1, the one we are using, when the CLK switch is set to high.
    5. Connect the Q output on pin 16 to the right LED.
    6. Connect the Q' output on pin 1 to the left LED.
      Figure \(\PageIndex{9}\): D latch using a 7475 chip

      Screen Shot 2020-06-27 at 2.55.20 AM.png

    This circuit should behave exactly like the circuit in Figure \(\PageIndex{6}\).

    \(\PageIndex{6}\) Limitations of the D latch

    The D latch does store state, but it is inefficient when implemented in a sequential circuit. To understand why it is inefficient, consider the Figure \(\PageIndex{10}\), which implements a circuit where the D latch provides some part of the state, and a black box containing some combinational logic to determine the next state. In this circuit, the result of that black box uses the current D input to determine the new state and set the D latch.

    Consider the case where the black box takes longer than a half of the clock pulse, as shown in Figure \(\PageIndex{10}\). The D latch retains its value until the combinational logic is completed, which occurs when the CLK is low. Thus the value of the D is not changed until the next clock pulse, and the circuit is fine.

    Figure \(\PageIndex{10}\): State transition with multiply operation

    Screen Shot 2020-06-27 at 3.02.42 AM.png

    However, it is unreasonable to expect all instances of combinational logic to take the same amount of time. For example, the time to do addition is very much smaller than the time it takes to do multiplication. This situation is shown in Figure \(\PageIndex{11}\). Here the black box can execute faster than the clock can pulse. In this case the latch is changed in the middle of a state transition, and the new value will cause the combinational logic to continue to process the new value while the clock pulse is low. Therefore, the value the D latch will be set to when the clock pulses high again will be incorrect.

    Figure \(\PageIndex{11}\): State transition with add operation

    Screen Shot 2020-06-27 at 3.04.35 AM.png

    One way to handle this situation is to put two D latches in the circuit, one which is set when the clock is high and the other when the clock is low, as shown in the Figure \(\PageIndex{12}\). This allows the circuit to obtain a value from the second D latch while updating the first.

    Figure \(\PageIndex{12}\): Two D latches to hold correct state

    Screen Shot 2020-06-27 at 3.06.42 AM.png

    While this solves the problem of maintaining the proper state of the latch, it should be obvious that it is a problem because it more than doubles the size of the circuit needed. This is twice as expensive, uses twice as much power, and produces twice as much heat. A better solution is needed, and one that was developed is called an edge triggered flip-flop.


    This page titled 9.3: Latches is shared under a CC BY 4.0 license and was authored, remixed, and/or curated by Charles W. Kann III via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.