# 11.8: Questions


1. What is the effect on output offset voltage as the voltage gain is increased?

2. Is the worst case $$V_{os}$$ a good approximation for the actual $$V_{os}$$? Explain.

3. Given the range of adjustment found in Table 11.7.3 along with the data from Tables 11.7.1 and 11.7.2, is it likely that the circuitry of Figure 11.5.1 will be sufficient to correct for the offset produced by a worst case op amp? Explain.

4. Based on the simulation results, is it safe to say that output DC offset is only affected by voltage gain and not the specific feedback resistor values used?

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