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Engineering LibreTexts

23.4: Procedure

  • Page ID
    37311
  • 23.4.1: Midband Response

    1. The circuit of Figure 23.3.1 is the same as the one used in the Common Emitter Amplifier exercise. The values used were Vcc = 15 volts, Vee = −12 volts, Rs = 10 k\(\Omega\), Rb = 33 k\(\Omega\), Re = 22 k\(\Omega\), Rc = 15 k\(\Omega\), Rload = 20 k\(\Omega\), C1 = C2 = 10 \(\mu\)F and C3 = 470 \(\mu\)F. It was shown that the amplifier produced considerable voltage at 1 kHz. Build the circuit using these values and verify that it is operating correctly by setting Vin to a 40 mV peak-peak sine wave at 1 kHz and measuring Vout. Compute the voltage gain and record these two values in Table 23.5.1.

    2. Compute the expected critical frequencies of the input and output coupling networks along with the emitter bypass network and record the values in Table 23.5.2. Include the Thevenized resistance for each equivalent circuit.

    23.4.2: Lower Frequency Limit

    3. The input coupling network can be made clearly dominant by replacing C1 with a smaller value. Decreasing C1 from 10 \(\mu\)F to 10 nF will increase its critical frequency by a factor of 1000. Replace C1 with this value.

    4. Set the AC source voltage to a 40 mV peak-peak 10 kHz sine wave. Note the output level at the load. Sweep the frequency between 5 kHz and 20 kHz to verify that the gain is stable. Decrease the input frequency until the load signal drops to 70.7% of the 10 kHz level. Record this value in Table 23.5.3.

    5. The output network may be examined in a similar fashion. Return C1 to 10 \(\mu\)F, replace C2 with a 10 nF and repeat step 4.

    6. Return C2 to the original 10 \(\mu\)F capacitor before proceeding.

    23.4.3: Upper Frequency Limit

    7. The upper frequency limit is controlled by small device and wiring capacitances that will vary with the precise components used and the circuit layout. To minimize potential errors, a large load capacitance can be shunted across Rload to bring the critical frequency down to an easily managed frequency. This could also represent the effect of cable capacitance.

    8. Place a 2.2 nF capacitor across the load. Compute the effective resistance of the lag network and its corresponding critical frequency in Table 23.5.4.

    9. Set the AC source voltage to a 40 mV peak-peak 1 kHz sine wave. Note the output level at the load. Sweep the frequency around 1 kHz to verify that the gain is stable. Increase the input frequency until the load signal drops to 70.7% of the 1 kHz level. Record this value in Table 23.5.4.

    23.4.4: Computer Simulation

    10. Perform an AC Analysis (Bode plot) of the amplifier using the original capacitor values and for the three variations. Plot the gain from 1 Hz to 10 MHz for the original circuit and from 10 Hz to 100 kHz for the three variations. Compare the simulated results to the experimental values.

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