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30.1: Theory Overview

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    37351
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    For small AC drain-source voltages (<100 mV) the JFET appears as a resistance from drain to source. This resistance is controlled by the DC gate to source voltage. This is referred to as the control voltage or \(V_C\). The more negative the potential, the larger the resistance. The minimum resistance will be achieved when \(V_{GS} = 0\). If \(V_{GS}\) is continuously variable then the JFET behaves as a rheostat, also called a voltage controlled resistor. The addition of a separate resistor in the drain will create a voltage controlled potentiometer. Unlike a true potentiometer, the output signal will not drop to zero due to the minimum on resistance of the JFET \((R_{ds(on)})\). Multiple units can be cascaded for increased attenuation. If the control voltage is set to achieve only the maximum and minimum values, the circuit behaves as a switch that allows or disallows the signal through. This is known as an analog switch.


    30.1: Theory Overview is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by James M. Fiore via source content that was edited to conform to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.