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30.4: Procedure

  • Page ID
    37354
  • 30.4.1: Voltage Controlled Divider

    1. Consider the circuit of Figure 30.3.1 where Vin is a 100 mV peak sine at 1 kHz, Ra = 4.7 k\(\Omega\) and Rg = 10 k\(\Omega\). As Vc varies between 0 and \(V_{GS(off)}\), the resistance of the JFET varies between a near open and a minimum value of \(R_{ds(on)}\). Vout is derived from a voltage divider between Ra and the JFET’s resistance.

    2. Build the circuit of Figure 30.3.1 with Ra = 4.7 k\(\Omega\) and Rg = 10 k\(\Omega\). Set Vin to 100 mV peak at 1 kHz. Set the control voltage, \(V_C\), to 0 VDC. Measure the signal at Vout using the oscilloscope and record the value in Table 30.5.1. Also, using the voltage divider rule, determine the effective resistance of the JFET.

    3. Repeat step 2 for the remaining control voltages listed in Table 30.5.1.

    4. Using the data from Table 30.5.1, create a plot of effective resistance versus control voltage.

    30.4.2: Analog Switch

    5. Build the circuit of Figure 30.3.2 with Ra = Rb = 4.7 k\(\Omega\) and Rg = 10 k\(\Omega\). Set Vin to 100 mV peak at 1 kHz. Set the control voltage, \(V_C\), to 0 VDC. Measure the signal at Vout using the oscilloscope and record the value in Table 30.5.2.

    6. Set the control voltage to −8 VDC, measure and record the output signal in Table 30.5.2. Based on these readings, determine the attenuations \((V_{out}/V_{in})\) and record the results in Table 30.5.2.

    30.4.3: Computer Simulation

    7. Repeat steps 2 and 3 using a simulator, recording the results in Table 30.5.3.