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DC biasing is required in order to maintain the proper junction potentials and operation of the BJT. Several different circuit configurations are available to establish a DC bias on both NPN and PNP transistors. These circuits vary in complexity and their ability to maintain a constant operating point, or Q point, in the face of variations of \(\beta\).
The two-supply emitter bias topology offers very high Q point stability. It achieves this through the use of two powers supplies; one connected through a resistor to the emitter and a second unit connected through a resistor to the collector. It is unique in that the supplies are bipolar; one being positive and the other being negative.
The voltage divider bias circuit offers similar stability performance to the two-supply emitter bias circuit. It uses a single supply and a resistive voltage divider to establish a second, lower potential at the base terminal.
The three feedback bias configurations offer only modest enhancements in stability but use the least amount of parts. They all rely on a single DC power source.
A DC load line is a plot of all possible collector current and corresponding collector-emitter voltage operating points. No matter what the \(\beta\) for a circuit happens to be, the transistor's operating point must lie on this line. It is a valuable DC analysis tool.
5.6.1: Review Questions
1. Explain the need for DC biasing. Why can't we just apply an AC signal to the base of a BJT and expect proper amplification of the signal?
2. What is a Q point?
3. What are the four values found on a DC load line?
4. Rank the bias configurations presented in this chapter in terms of their Q point stability relative to \(\beta\).
5. Rank the bias configurations presented in this chapter in terms of their circuit complexity.
6. Describe the process of making a PNP version of an NPN bias circuit.