3.1: Overview of the Machine Code Instruction Format
- Page ID
- 27252
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\(\newcommand{\avec}{\mathbf a}\) \(\newcommand{\bvec}{\mathbf b}\) \(\newcommand{\cvec}{\mathbf c}\) \(\newcommand{\dvec}{\mathbf d}\) \(\newcommand{\dtil}{\widetilde{\mathbf d}}\) \(\newcommand{\evec}{\mathbf e}\) \(\newcommand{\fvec}{\mathbf f}\) \(\newcommand{\nvec}{\mathbf n}\) \(\newcommand{\pvec}{\mathbf p}\) \(\newcommand{\qvec}{\mathbf q}\) \(\newcommand{\svec}{\mathbf s}\) \(\newcommand{\tvec}{\mathbf t}\) \(\newcommand{\uvec}{\mathbf u}\) \(\newcommand{\vvec}{\mathbf v}\) \(\newcommand{\wvec}{\mathbf w}\) \(\newcommand{\xvec}{\mathbf x}\) \(\newcommand{\yvec}{\mathbf y}\) \(\newcommand{\zvec}{\mathbf z}\) \(\newcommand{\rvec}{\mathbf r}\) \(\newcommand{\mvec}{\mathbf m}\) \(\newcommand{\zerovec}{\mathbf 0}\) \(\newcommand{\onevec}{\mathbf 1}\) \(\newcommand{\real}{\mathbb R}\) \(\newcommand{\twovec}[2]{\left[\begin{array}{r}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\ctwovec}[2]{\left[\begin{array}{c}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\threevec}[3]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\cthreevec}[3]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\fourvec}[4]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\cfourvec}[4]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\fivevec}[5]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\cfivevec}[5]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\mattwo}[4]{\left[\begin{array}{rr}#1 \amp #2 \\ #3 \amp #4 \\ \end{array}\right]}\) \(\newcommand{\laspan}[1]{\text{Span}\{#1\}}\) \(\newcommand{\bcal}{\cal B}\) \(\newcommand{\ccal}{\cal C}\) \(\newcommand{\scal}{\cal S}\) \(\newcommand{\wcal}{\cal W}\) \(\newcommand{\ecal}{\cal E}\) \(\newcommand{\coords}[2]{\left\{#1\right\}_{#2}}\) \(\newcommand{\gray}[1]{\color{gray}{#1}}\) \(\newcommand{\lgray}[1]{\color{lightgray}{#1}}\) \(\newcommand{\rank}{\operatorname{rank}}\) \(\newcommand{\row}{\text{Row}}\) \(\newcommand{\col}{\text{Col}}\) \(\renewcommand{\row}{\text{Row}}\) \(\newcommand{\nul}{\text{Nul}}\) \(\newcommand{\var}{\text{Var}}\) \(\newcommand{\corr}{\text{corr}}\) \(\newcommand{\len}[1]{\left|#1\right|}\) \(\newcommand{\bbar}{\overline{\bvec}}\) \(\newcommand{\bhat}{\widehat{\bvec}}\) \(\newcommand{\bperp}{\bvec^\perp}\) \(\newcommand{\xhat}{\widehat{\xvec}}\) \(\newcommand{\vhat}{\widehat{\vvec}}\) \(\newcommand{\uhat}{\widehat{\uvec}}\) \(\newcommand{\what}{\widehat{\wvec}}\) \(\newcommand{\Sighat}{\widehat{\Sigma}}\) \(\newcommand{\lt}{<}\) \(\newcommand{\gt}{>}\) \(\newcommand{\amp}{&}\) \(\definecolor{fillinmathshade}{gray}{0.9}\)All machine code instructions for our computer will consist of two 4-bit segments, and one 8-bit segment, as shown below.
The first 4-bit segment will represent the type of operation. The possible types of operations are the following:
- 1 –This opcode represents an immediate operation which uses the ALU to produce a result. This instruction consists of the 4-bit opcode, a 4-bit ALU option (ALUopt) to tell the ALU what operation to execute, and an 8 bit data immediate value for an operand. As implemented the ALU only executes 2 operations, 0x0 is add and 0x1 is subtract, though the exercises at the end of the text add more operations. A maximum of 16 operations can be implemented in the CPU.
Examples of translating these assembly instructions into machine code follow.
The instruction:
addi 2
translates into the following machine code:
0x1002
The instruction:
subi 15
translates to the following machine code
0x110f
- 2 – This opcode represents a memory address operation which uses the ALU to produce a result. This instruction consists of the 4-bit opcode, a 4-bit ALUopt to tell the ALU what operation to execute, and an 8 bit data memory address for an operand. As implemented the ALU only executes 2 operations, 0x0 is add and 0x1 is subtract, though the exercises at the end of the text add more operations. A maximum of 16 operations can be implemented in the CPU.
Examples of translating these assembly instructions into machine code follow.
The instruction:
add 2
translates into the following machine code:
0x2002
The instruction
sub 15
translates into the following machine code
0x210f
Note that during assembly process labels in assembly code are translated into addresses, so labels will never appear in machine code.
- 3 – This opcode executes the clac operation (e.g. it sets the
$ac
to 0). In this instruction all of the subsequent bits after the 0x3 are ignored, so they can contain any value. By convention, the extra bits should always be set to 0.For example, the following assembly instruction
clac
translates to
0x3000
- 4 – This opcode executes the stor operation. In this instruction the 4 bit ALU opt is not used, and should be set to 0. The address value is the address at which to store the value in the
$ac
. For example, the following instructionstor 15
translates to:
0x400f
- 0x5 – The opcode executes the beqz operation. In this instruction the 4 bit ALU operation is not used, and should be set to blank. The result of this operation is the
$pc
is set to the address value if the$ac
is zero. Setting the value for the$pc
causes the program to branch to that address.For example, the following instruction
beqz 40
translates to:
0x5028