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5.8: The temperature dependence of current in the OFF state

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    51619
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    Both nanoscale and larger transistors have a small quantum capacitance in the OFF state, which is also known as subthreshold since \(V_{GS} < V_{T}\).

    But even if the density of states is zero between \(\mu_{S} > E > \mu_{D}\), at higher temperatures, some electrons may be excited into empty states well above the Fermi Energy. If the density of states is very low at the Fermi Energy, but higher far from the Fermi level, then we can model the Fermi distribution by an exponential tail. Recall that this is known as a non-degenerate distribution; see Figure 5.8.1.

    Screenshot 2021-05-18 at 18.21.46.png
    Figure \(\PageIndex{1}\): If only the extreme tail states of the Fermi distribution are filled, then we can model the distribution by an exponential. This is common when the density of states at the Fermi Energy is small.

    Equation (5.5.3) becomes

    \[ N_{S} = \int^{\infty}_{-\infty} g(E-U)e^{-(E-\mu_{S})/kT}dE \nonumber \]

    Now changing the variable of integration to \(E’=E-U\)

    \[ N_{S} = \int^{\infty}_{-\infty} g(E’)e^{-(E’+U-\mu_{S})/kT}dE’ \nonumber \]

    Simplifying

    \[ N_{S} = e^{-U/kT}\int^{\infty}_{-\infty} g(E’)e^{-(E’-\mu_{S})/kT}dE’ \nonumber \]

    Similarly,

    \[ N_{D} = e^{-U/kT}\int^{\infty}_{-\infty} g(E’)e^{-(E’-\mu_{D})/kT}dE’ \nonumber \]

    Thus, from Eq. (5.5.3) the current is

    \[ I = \frac{q}{\tau}\text{exp}\left[\frac{qV_{GS}}{kT} \right] \cdot \int^{\infty}_{-\infty} g(E’)\left( e^{-(E’-\mu_{S})/kT} - e^{-(E’-\mu_{D})/kT}\right) \nonumber \]

    Equation (5.8.5) holds in the limit that \(C_{G} \gg C_{S}, C_{D}\). In general, we find that the current in the subthreshold region is

    \[ I = I_{0}\text{exp}\left[\frac{qV_{GS}}{kT} \frac{C_{G}}{C_{ES}}\right] \nonumber \]

    Taking logarithm of both sides we find,

    \[ \text{log}_{10}I=\frac{q}{KT}\frac{C_{G}}{C_{ES}}(\text{log}_{10}e)V_{GS}+\text{log}_{10}I_{0} \nonumber \]

    The slope, S, of the subthreshold regime is usually expressed gate volts per decade of drain current. At room temperature, the optimum, when \(C_{G} \gg C_{S}, C_{D}\), is

    \[ S=\frac{kT}{q}\frac{1}{\text{log}_{10}e} \approx 60 \text{ mV/decade} \nonumber \]

    The slope becomes much sharper at low temperatures; see Figure 5.8.2.

    Screenshot 2021-05-18 at 18.37.06.png
    Figure \(\PageIndex{2}\): A comparison of the switching characteristics of our C60 model FET at T = 1K and room temperature. In the OFF regime, the current varies exponentially with gate bias, i.e. a straight line on a log-linear plot. The slope at room temperature is 60 mV/decade of drain current.

    This page titled 5.8: The temperature dependence of current in the OFF state is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by Marc Baldo (MIT OpenCourseWare) via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.