7.7: The future of electronics?

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The immediate path is clear: we have not yet reached the limits of scaling, or the fundamental limits of field effect transistors. The electronics industry will push to smaller length scales to minimize the power delay product. It will also seek to exploit ballistic conduction in low dimensional materials, thereby increasing switching speeds.

It is realistic to expect that a future MOSFET might possess:

ballistic transport and operation at the quantum limit of conductance
switching on and off at the optimum FET subthreshold slope of kT/q
scaling of all dimensions with a gate insulator thickness of ~ 1 nanometer

Traditionally, substantial materials development efforts have been devoted to improving the mobility of transistor channels. But because devices are already at the ballistic limit, the electrostatic design of nanotransistors will be a likely focus of materials development. We have seen that good electrostatic control of the channel can be achieved by maximizing the gate capacitance. For example, with a nanowire channel, the gate could be implemented as a concentric ring. Or a channel that consists of a single atomic layer (such as a grapheme sheet) might be preferable from the electrostatic viewpoint to a thicker layer of silicon, even though both will operate at the ballistic limit. Manufacturing such advanced structures may require a substantial amount of further development.

Beyond this, there appears to be only one major weakness of conventional FET technologies. There is a strong possibility that new technologies will demonstrate subthreshold slope far superior to kT/q. As we have seen, this will allow for dramatic reductions in operating voltage, and hence significantly lower power dissipation.

From a fundamental viewpoint, all transistors that operate in thermodynamic equilibrium, must exhibit an energy difference between their ON and OFF states. For example, the potential energy difference between the ON and OFF states of a FET is \(\Delta E = \frac{1}{2}CV^{2}\), which can also be expressed as \(\Delta E = \frac{1}{2}QV\), where Q is the total charge on the gate capacitor and V is the supply voltage. The fundamental limit in the OFF state current is the probability of thermal excitation from the OFF state to the ON state. That is:

\[ I_{OFF} = I_{ON}\exp \left[-\frac{1}{2}QV/kT \right] \label{7.7.1} \]

where \(I_{ON}\) is the maximum current associated with the ON state. But as we have seen, modern FETs do not operate at this limit because each electron in the channel is independent. In contrast to Equation \ref{7.7.1}, the FET follows:

\[ I_{OFF} = I_{ON}\exp \left[-qV/kT \right] \label{7.7.2} \]

Except for a FET that operates with a single electron in the channel, the difference is substantial: a subthreshold slope of kT/Q versus kT/q. Indeed, at present transistor dimensions \(Q \gg 10^{3}q\).