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9.1: CIRCUIT DESCRIPTION

  • Page ID
    58465
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    The purpose of this section is to illustrate by example one way that the basic two-stage amplifier can be expanded into a complete, useful opera­tional amplifier. Later sections of this chapter analyze the circuit to deter­mine its performance, show how it can be compensated in order to tailor its open-loop transfer function for use in specific applications, and indicate how design alternatives might affect performance.

    No attempt is made to justify this particular implementation of the two-stage amplifier other than to point out that the circuit was designed at least in part for its educational value. An appreciation of the salient fea­tures of this particular circuit leads directly to improved understanding of other operational amplifiers, including a number of integrated-circuit de­signs, which have evolved from the basic topology. The modifications in­corporated into the basic design are certainly not the only possible ones, nor are they all likely to be required in any given application. The circuit does illustrate how a designer might resolve some of the tradeoffs available to him, and also provides a background for much of the material in later sections.

    Overview

    截屏2021-08-16 下午9.00.13.png
    Figure 9.1 Discrete-component operational amplifier. Note. Indicates 1% metal-film resistor.

    The complete circuit and important quiescent levels are shown in Figure 9.1. The circuit represents a modification of the basic amplifier that com­bines a differential amplifier incorporating several of the drift minimizing techniques described in Chapter 7 with a high-gain stage consisting of a current-source-loaded cascode amplifier. A unity-voltage-gain buffer ampli­fier isolates the high-resistance node at the output of the cascode amplifier and provides high current output drive capability. The amplifier is designed to provide a \(\pm 10-\text{volt}\) maximum output signal and operate from standard \(\pm 15-\text{volt}\) supplies. The supply voltages are both bypassed with a parallel combination of an electrolytic and a ceramic capacitor, since this combina­tion is effective over a wide frequency range.

    This circuit shares a characteristic with a number of other moderately involved designs, which is often disturbing to novice circuit designers since there is some difficulty in determining which transistors are actually in the signal path. It is important to resolve this uncertainty prior to any detailed discussion of the circuit. Referring to Figure 9.1, we see that transistors \(Q_1\) and \(Q_2\) are the differential-amplifier input stage. As we shall see, the second-stage topology constrains the emitter connection of the \(Q_4-Q_5\) pair to be incrementally grounded. Thus \(Q_5\) and \(Q_6\) form a cascode amplifier. This current-source-loaded cascode provides the largest fraction of the amplifier gain, with analysis to be presented indicating a voltage gain of 180,000 in this portion of the circuit.

    The high-resistance node at the output of the cascode amplifier is iso­lated with source-follower-connected FET \(Q_8\). The source follower drives transistors \(Q_{10}\) and \(Q_{11}\), which are connected as a complementary emitter follower.

    The amplifier can be compensated by connecting an appropriate net­ work between the indicated terminals, thereby forming a minor loop that includes the high-gain stage. Details of this process are given in Section 9.2.3.

    The above discussion shows that the signal path includes only transistors \(Q_1, Q_2, Q_5, Q_6, Q_8, Q_{10}\), and \(Q_{11}\). The remaining transistors are used either as current sources (\(Q_3\), \(Q_7\), and \(Q_9\)), or to reduce voltage drift referred to the input by forming a differential second stage at d-c (\(Q_4\)), or to limit out­put current (\(Q_{12}\) and \(Q_{13}\)).

    Detailed Considerations

    Once the topology of the circuit is selected, a decision concerning approxi­mate bias-current levels is a necessary first step in the detailed design process. Low current levels give improved d-c performance since input currents and input-stage self-heating are reduced. However, the frequency response of the amplifier is reduced by operation at low currents. (See Section 9.3.3 for a description of power-speed tradeoffs.)

    A compromise collector current level of \(10\ \mu A\), which can provide ex­cellent d-c performance combined with closed-loop frequency response of several MHz, was selected for the first-stage transistors. Transistor \(Q_3\) is a current source that provides the total \(20-\mu A\) quiescent current of the first stage and insures high common-mode rejection ratio. This current source shares a common bias network with two other current sources. The bias network includes a diode that provides approximate temperature compen­sation for the current sources, and also includes capacitive bypassing to the negative supply. Bypassing to the negative supply rather than to ground is preferable in this case since it insures that the current-source output is independent of high-speed transients on the negative supply line.

    The differential input stage is a matched pair of 2N5963 transistors. The devices are selected to have base-to-emitter voltages matched to within 3 mV at equal collector currents and, furthermore, to have current gains matched to within 10% at the operating current level. They are mounted in close thermal proximity to reduce temperature differentials. Wrapping wire around the pair or mounting them in an aluminum block drilled to accept the transistors improves the thermal bond. The 2N5963 is selected because it is inexpensive and provides a typical current gain of 1100 at a collector current of \(10 \mu A\). The resultant bias current required at either input is approximately \(10\ nA\) without any form of current compensation. Compen­sating techniques such as these described in Section 7.4.2 can be used to lower this bias current to less than \(1\ nA\) over a \(50^{\circ} C\) temperature range.

    Transistors \(Q_5\) and \(Q_6\) are the cascode-amplifier transistors. An additional PNP transistor, \(Q_4\), is used to improve d-c performance by forming a differ­ential amplifier with transistor \(Q_5\). While this transistor lowers drift, it does not affect the operation of the \(Q_5-Q_6\) pair in any way as shown by the fol­lowing discussion. It is evident that at low frequencies the common-emitter point of pair \(Q_4-Q_5\) is incrementally grounded since only differential signals

    can be applied to this pair by the input stage. The capacitor(As a matter of practical interest, eliminating this capacitor has only a minor effect on the overall performance of the amplifier, but complicates the analysis. This is an example of a component included primarily for educational purposes.) included across the \(33-k\Omega\) emitter-circuit resistor guarantees that the emitter of \(Q_5\) also re­mains incrementally grounded at high frequencies. Since transistor \(Q_4\) is included only to improve d-c performance and is not required for gain at any frequency, its base circuit can be bypassed at moderate and high fre­quencies. Bypassing insures that \(Q_1\) operates as a common-collector stage at these frequencies. It was mentioned in the last chapter that operation in this mode is advantageous since it minimizes the input capacitance seen at the base of \(Q_1\) (the inverting input of the complete amplifier), and thus allows a wider range of feedback networks to be used without significant high-frequency loading.

    The amplifier is balanced by changing relative collector load resistor values in the first stage. Since the input-stage transistors are matched for a maximum base-to-emitter voltage differential of 3 mV at equal collector currents, the ratio of the collector currents will be at most \(e^{3mV(q/kT)} \simeq 1.12\) at equal base-to-emitter voltages. The \(50-k\Omega\) potentiometer that allows a maximum collector-resistor ratio of 1.17:1 is therefore adequate for bal­ancing even if some mismatch of second-stage base currents exists. The diode included in the \(Q_1-Q_2\) collector circuit provides a degree of com­pensation for the base-to-emitter voltage changes of transistors \(Q_4-Q_5\) with temperature in order to stabilize their quiescent current.

    The 2N4250 transistors used in the second stage are one of the highest-gain PNP types available, with a typical current gain in excess of 300 at \(50\ \mu A\) of collector current. This gain permits a five-to-one increase in quiescent operating level between the first and second stages (valuable since this in­crease improves the bandwidth of the second-stage devices) without seri­ously compromising drift performance. It also contributes to high overall amplifier gain. While it is not necessary to use the same transistor type for both members of a cascode amplifier pair, the 2N4250 is also used in the common-base section of the cascode (\(Q_6\)) since it has high \(r_{\mu}\), a necessary condition for high voltage gain. The 2N3707 used as the current-source load for the cascode is also selected in part because of high \(r_{\mu}\).

    All critical resistors associated with the first two stages are precision metal film types. These are preferred since their low temperature coeffi­cients reduce voltage drift and because of their low noise characteristics.

    A field-effect transistor is used to isolate the high-impedance node at the cascode output. The virtually infinite input resistance of the FET improves voltage gain. Component economy is also achieved, since an additional stage of current gain would probably be required for isolation if bipolar transistors were used. A current source is used for FET bias so that the bias current is independent of output-voltage level. The quiescent level of this stage is chosen to meet maximum drive requirements for the following stage.

    A complementary emitter-follower pair (\(Q_{10}-Q_{11}\)) is used to provide large positive or negative output currents with minimum quiescent power dissi­pation. Metal-can rather than epoxy-cased transistors are used in this stage for increased power-handling capability. The two diodes included in the base circuit of the emitter-follower pair reduce crossover distortion, while the \(22-\Omega\) resistors eliminate the possibility of thermal runaway that accom­panies this connection.

    Transistors \(Q_{12}\) and \(Q_{13}\) combine with the \(22-\Omega\) resistors to limit the out­ put current of the amplifier to approximately \(30\ mA\). This limiter circuit, which is similar in operation to the diode limiter described in connection with Figure 8.27, is used since it is identical in form to one frequently used in integrated-circuit designs. Consider'the limiting process when the amplifier output voltage is negative. If the sink current exceeds 25 to \(30\ mA\), tran­sistor \(Q_{13}\) conducts, since its base-to-emitter voltage approximates 600 mV. This conduction reduces base drive for \(Q_{11}\). The current that must be con­ducted by \(Q_{13}\) in order to eliminate base drive to \(Q_{11}\) is at most \(2\ mA\), the output level of current source \(Q_9\).

    When the amplifier output voltage is positive, transistor \(Q_{12}\) conducts to limit output current. This situation is potentially hazardous, since it is conceivable that the driving transistor (\(Q_8\)) could be destroyed if no mechanism limited its drain current. However, the geometry of the TIS58 is such that its drain current is the order of \(5\ mA\) when the gate-to-source voltage of this device reaches the forward-conduction value. Thus, while transistor \(Q_{12}\) may conduct approximately \(3\ mA\) in positive output current limit, destruction of \(Q_8\) is not possible. Note also that since the maximum collector current of \(Q_6\) is limited to modest values by the \(33-k\Omega\) emitter-circuit resistor associated with \(Q_4-Q_5\), the maximum current from \(Q_6\), cannot injure any devices.

    No attempt is made to control internal amplifier voltages, such as the emitter potential of \(Q_5\), during current overload. The charge stored on the \(3.3-\mu F\) capacitor delays recovery from overload, but since current limit is not anticipated during normal operation (overload protection is included primarily to protect us from our own errors during system breadboarding), this delay is unimportant.


    This page titled 9.1: CIRCUIT DESCRIPTION is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by James K. Roberge (MIT OpenCourseWare) via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.