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9.5.9: Integrated Circuit Manufacturing - A Bird's-Eye View

  • Page ID
    89989
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    It will no doubt be helpful if we also take a plane or "bird's eye" view of what this circuit looks like. There are, in fact, some interesting things we can gain by looking at some of these views.

    We have been looking at the development of the circuit from a cross-sectional point of view, watching the formation of the various levels which make up the finished CMOS inverter. This is, in fact, not the way a circuit designer looks at things. A circuit designer sees things from above, and only worries about the placement of transistors, and how they will be connected together. In fact, the only factor in the actual design of the layout engineer has any choice on is the transistor width, \(W\). All other parameters are decided upon beforehand by the process engineer. So what does the layout engineer see? We start with the n-implant to make the n-tank, as shown in Figure \(\PageIndex{1}\). (You should go back and follow along with the cross-sectional views of the process, as we review looking at things from the top.)

    Top-down view of a n-tank, represented as a square.
    Figure \(\PageIndex{1}\): Implanted n-tank

    A mask opposite to that of the n-tank allows us to an n-channel \(V_{T}\) adjust. We next deposit and pattern the nitride for the active regions, and grow the field oxide (FOX) layer as shown in Figure \(\PageIndex{2}\).

    Top-down view of the silicon wafer, represented as a large rectangle with the n-tank on the right side. This is overlaid with a layer of FOX over the whole wafer, and in the foreground are two smaller squares of nitride: one on the right half, inside the n-tank, and one on the left half.
    Figure \(\PageIndex{2}\): Growing FOX

    We remove the nitride, and deposit and pattern the polysilicon, as seen in Figure \(\PageIndex{3}\).

    The wafer from Figure 2 above has the nitride layer removed and a layer of polysilicon, shaped like two narrow vertical rectangles, located over the squares previously covered by nitride, joined by a horizontal bar with a small protrusion at its bottom center.Figure \(\PageIndex{3}\): Gate poly pattern

    Figure \(\PageIndex{4}\) shows what the two masks look like for the n+ and p+ source/drain implants:

    The wafer from Figure 3 above has an n+ implant, shaped like a small square with an unconnected rectangle on its left, and a p+ implant, shaped like a small square with a unconnected rectangle on its right. The implants are located on the squares previously occupied by the nitride on the left and the right, respectively.
    Figure \(\PageIndex{4}\): S/D Implants

    Note that the gate poly extends beyond where the implant is being performed (inside the dotted line). This is a design rule which is the way the circuit designer takes into account the fact that the manufacturing process must have some tolerance built in, because things will not always be lined up just perfectly. Now we make some contact holes, seen in Figure \(\PageIndex{5}\):

    Two holes are cut on either side of each vertical arm of the polysilicon layer, within the boundaries of the implant square. A hole is also cut in each of the small unconnected rectangles of the implants.Figure \(\PageIndex{5}\): Etching contact holes

    And finally, we sputter and pattern the metallization, which is depicted in Figure \(\PageIndex{6}\). You should go back to MOSFETs, and convince yourself that the circuit shown in Figure \(3.10.4\) is indeed what has been constructed in Figure \(\PageIndex{6}\). See if you can identify all of the correct parts. Note that there is a connection between \(V_{\text{ss}}\) (ground) and the p-substrate very close to the n-channel source. There is also a contact between the n-moat and \(V_{\text{dd}}\), which is very close to the p-channel source. What advantage would this have? Hint: review the discussion of latch-up.

    Metal regions are added to the wafer from Figure 5 above. One connects the two holes on the left of the left vertical poly strip, extending beyond the left edge of the wafer and forming a contact for V_ss. Another metal region connects the two holes to the right of the right vertical poly strip, extending beyond the right edge of the wafer and forming a contact for V_dd. A third metal region connects the two holes in between the vertical poly strips and extends upward beyond the edge of the wafer, forming a contact for V_out. The small protrusion from the bottom of the horizontal arm of the polysilicon region forms a contact for V_in.Figure \(\PageIndex{6}\): Metallization patterning

    This page titled 9.5.9: Integrated Circuit Manufacturing - A Bird's-Eye View is shared under a CC BY-NC-SA 1.0 license and was authored, remixed, and/or curated by Bill Wilson via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.