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1.6: The Differential Amplifier

  • Page ID
    3549
  • Most modern operational amplifiers utilize a differential amplifier front end. In other words, the first stage of the operational amplifier is a differential amplifier. This circuit is commonly referred to as a diff amp or as a long-tailed pair. A diff amp utilizes a minimum of 2 active devices, although 4 or more may be used in more complex designs. Our purpose here is to examine the basics of the diff amp so that we can understand how it relates to the larger operational amplifier. Therefore, we will not be investigating the more esoteric designs. To approach this in an orderly fashion, we will examine the DC analysis first, and then follow with the AC small signal analysis.

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    DC Analysis

    A simplified diff amp is shown in Figure 1.17. This circuit utilizes a pair of NPN bipolar transistors, although the circuit could just as easily be built with PNPs or FETs. Note the inherent symmetry of the circuit. If you were to slice the circuit in half vertically, all of the components on the left half would have a corresponding component on the right half. Indeed, for optimal performance, we will see that these component pairs should have identical values. For critical applications, a matched pair of transistors would be used. In this case, the transistor parameters, such as \(β\), would be very closely matched for the two devices.

    In Figure 1.18, the circuit currents are noted, and the generalized current source has been replaced with a resistor/negative power supply combination. This is in essence, an emitter bias technique. Assuming that the base voltages are negligible and that \(V_{BE}\) is equal to 0.7 V, we can see that the emitter of each device is at approximately -0.7 V. Kirchhoff’s Voltage Law indicates that the bulk of the negative supply potential must drop across \(R_T\).

    $$ V_{RT} =∣V_{EE}∣−.7V \notag $$

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    Knowing this, we may find the current through \(R_T\), which is known as the tail current, \(I_T\).

    $$ I_T = \frac{∣V_{EE}∣−0.7 V}{R_T} \notag $$

    If the two halves of the circuit are well matched, the tail current will split equally into two portions, \(I_{E1}\) and \(I_{E2}\). Given identical emitter currents, it follows that the remaining currents and voltages in the two halves must be identical as well. These potentials and currents are found through the application of Kirchhoff’s Voltage and Current Laws just as in any other transistor bias analysis.

     

    Example 1.18

    Find the tail current, the two emitter currents, and the two collector to ground voltages in the circuit of Figure 1.19. You may assume that the two transistors are very closely matched.

    The first step is to find the tail current:

    $$ I_T = \frac{∣V_{EE}∣−0.7 V}{R_T} \notag $$

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    The tail current is the combination of the two equal emitter currents, so

    $$ \begin{align} &I_{EI} = I_{E2} = I_{T2} \notag \\   &I_{EI} = I_{E2} = \frac{4.65\ mA}{2} \notag \\ &I_{EI} = I_{E2} = 2.325\ mA \notag \end{align} \notag $$

     

    If we make the approximation that collector and emitter currents are equal, we may find the collector voltage by calculating the voltage drop across the collector resistor, and subtracting the result from the positive power supply.

    $$ \begin{align} V_{c} &= V_{cc} - I_c\ R_c \notag \\   V_{c} &= 20\ V - 2.325\ mA × 3kΩ  \notag \\ V_{c} &= 20\ V - 6.975\ V \notag \\ V_{c} &= 13.025\ V \notag\end{align} \notag $$

     

    Again, because we have identical values for both halves of the circuit, \(V_{C1} = V_{C2}\) . If we continue with this and assume a typical \(β\) of 100, we find that the two base currents are identical as well.

    $$ \begin{align} I_{B} &= \frac{I_c}{β} \notag \\   I_{B} &= \frac{2.325\ mA}{100}  \notag \\ I_{B} &= 23.25\ μA \notag\end{align} \notag $$

     

    Noting that the base currents flow through the 5 kΩ base resistors, we may find the base voltages. Note that this is a negative potential because the base current is flowing from ground into the transistor’s base.

    $$ \begin{align} V_{B} &= -I_b\ R_B \notag \\   V_{B} &= −23.25\ μA × 5kΩ  \notag \\  V_{B} &= −116.25\ mV \notag\end{align} \notag $$

     

    This result indicates that the actual emitter voltage is closer to -0.8 V than -0.7 V, and thus, the tail current is actually a little less than our approximation of 4.65 mA. This error is probably within the error we can expect by using the 0.7 V junction potential approximation.

     

    Input Offset Current and Voltage

    As you have no doubt guessed, it is impossible to make both halves of the circuit identical, and thus, the currents and voltages will never be exactly the same. Even a small resistor tolerance variation will cause an upset. If the base resistors are mismatched, this will cause a direct change in the two base potentials. A variation in collector resistance will cause a mismatch in the collector potentials. A simple \(β\) or \(V_{BE}\) mismatch can cause variations in the base currents and base voltages, as well as smaller changes in emitter currents and collector potentials. It is desirable then to quantify the circuit’s performance so that we can see just how well balanced it is. We can judge a diff amp’s DC performance by measuring its input offset current and its input and output offset voltages. In simple terms, the difference between the two base currents is the input offset current. The difference between the two collector voltages is the output offset voltage. The DC potential required at one of the bases to counteract the output offset voltage is called the input offset voltage (this is little more than the output offset voltage divided by the DC gain of the amplifier). In an ideal diff amp all three of these factors are equal to 0. We will take a much closer look at these parameters and how they relate to operational amplifiers in later chapters. For now, it is only important that you understand that these inaccuracies exist, and what can cause them.

     

    AC Analysis

    Figure 1.20 shows a typical circuit with input and output connections. In order to minimize confusion with the DC circuit, AC equivalent values will be shown in lower case. Small emitter degeneration resistors, \(r_{E1}\) and \(r_{E2}\), have been added to this

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    diff amp. This circuit has two signal inputs and two signal outputs. It is possible to configure a diff amp so that only a single input and/or output is used. This means that there are four variations on the theme:

    • Differential (also called dual- or double-ended) input, differential output.
    • Differential input, single-ended output.
    • Single-ended input, differential output.
    • Single-ended input, single-ended output.

    These variations are shown in Figure 1.21. For use in operational amplifiers, the differential input/single-ended output variation is the most common. We will examine the most general case, the differential input/differential output version.

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    Because the diff amp is a linear circuit, we can use the principle of Superposition to independently determine the output contribution from each of the inputs. Utilizing the circuit of Figure 1.20, we will first determine the gain equation from \(V_{in1}\) to either output. To do this, we replace \(V_{in2}\) with a short circuit. The AC equivalent circuit is shown in Figure 1.22.

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    For the output on collector 1, transistor 1 forms the basis of a common emitter amplifier. The voltage across \(r_{C1}\) is found via Ohm’s Law.

    $$ v_{r_{C1}} =−i_{C1}\ r_{C1} \notag $$

    The negative sign comes from the fact that AC ground is used as our reference. (i.e., for a positive input, current flows from AC ground down through \(r_{C1}\), and into the collector.) To a reasonable approximation, we can say that the collector and emitter currents are identical.

    $$ v_{r_{cl}} =−i_{EI}\ r_{C1} \notag $$

    We must now determine the AC emitter current in relation to Vin1. In order to better visualize the process, the circuit of Figure 1.22 is altered to include simplified transistor models, as shown in Figure 1.23.

     

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    \(r^{'}_e\) is the dynamic resistance of the base emitter junctions and is inversely proportional to the DC emitter current. You may recall the following equation from your prior course work:

    $$ r^{'}_e= \frac{26\ mV}{I_E} \notag $$

    Where \(r^{'}_e\) is the dynamic base-emitter junction resistance, \(I_E\) is the DC emitter current.

     

    For typical circuits, the values of \(r^{'}_e\) and \(r_E\) are much smaller than the tail current biasing resistor, \(R_T\). Because of its large size, we can ignore the parallel effect of \(R_T\). By definition, the AC emitter current must equal the AC emitter potential divided by the AC resistance in the emitter section. If you trace the signal flow from the base of transistor 1 to ground, you find that it passes through \(r^{'}_{e1}\),\(r_{E1}\), \(r^{'}_{e2}\) and \(r_{E2}\). You will also notice that the magnitude of \(i_{E1}\) is the same as \(i_{E2}\) , although they are out of phase.

    $$ i_E = \frac{v_{in1}}{ r^{'}_{e1}+r_{E1}+r^{'}_{e2}+r_{E2}} \notag $$

    Because the circuit values should be symmetrical for best performance, this equation may be simplified to

    $$ i_E = \frac{v_{in}}{ 2(r^{'}_{e}+r_{E})} \notag $$

    If we now solve for voltage gain,

    $$ A_v = -\frac{v_{out}}{v_{in}} \notag $$

    $$ A_v = \frac{-i_E\ r_c}{v_{in}} \notag $$

    $$ A_v = \frac{\frac{v_{in}}{2(r^{'}_{e}+r_{E})} r_c}{v_{in}} \notag $$

    $$ A_v = \frac{-r_c}{2(r^{'}_{e}+r_{E})} \notag $$

    Where \(A_v\) is the voltage gain, \(r_C\) is the AC equivalent collector resistance, \(r_E\) is the AC equivalent emitter resistance, \(r^{'}_{e}\) is the dynamic base-emitter junction resistance.

     

    The final negative sign indicates that the collector voltage at transistor number 1 is 180 degrees out of phase with the input signal. Earlier, we noted that i_{E2} is the same magnitude as i_{E1}, the only difference being that it is out of phase. Because of this, the magnitude of the collector voltage at transistor number 2 will be the same as that on the first transistor. Because the second current is out of phase with the first, it follows that the second collector voltage must be out of phase with the first. This means that the voltage at the second collector is in phase with the first input signal. Its gain equation is

    $$ A_v = \frac{r_c}{2(r^{'}_{e}+r_{E})} \notag $$

    The various waveforms are depicted in Figure 1.24. The preceding equation is often referred to as the single-ended input/single-ended output gain equation because it describes the single change from one input to one output. The output signal will be in phase if we are examining the opposite transistor, and out of phase if we are looking at the input transistor. Because the circuit is symmetrical, we will get similar results when we examine the second input. The voltage between the two collectors is 180 degrees apart. If we were to use a differential output, that is, derive the output from collector to collector rather than from one collector to ground, we would see an effective doubling of the output signal. If the reason for this is not clear to you, consider the following. Assume that each collector has a 1 V peak sine wave riding on it. When collector 1 is at +1 V, collector 2 is at -1 V, making +2 V total. Likewise, when collector 1 is at its negative peak, collector 2 is at its positive peak, producing a total of -2 V. The single ended input/differential output gain therefore is

    $$ A_v = \frac{r_c}{r^{'}_{e}+r_{E}} \notag $$

     

    Example 1.19

    Using the circuit of Figure 1.20, determine the single-ended input/differential output and single-ended input/single-ended output voltage gains. Use the following component values: \(V_{CC} =15V\), \(V_{EE} =-8V\) , \(R_T=10kΩ\), \(R_C=8kΩ\), \(r_E=30Ω\). In order to find \(r^{'}_e\) we must find the DC current.

     

    $$ \begin{align} I_{T} &= \frac{∣V_{EE}∣−0.7 V}{R_T} \notag \\   I_{T} &= \frac{7.3\ V}{10\ kΩ}  \notag \\ I_{T} &= 730\ μA \notag\end{align} \notag $$

    $$ \begin{align} I_{E} &= \frac{I_T}{2} \notag \\   I_{E} &= \frac{730\ μA}{2}  \notag \\ I_{E} &= 365\ μA \notag\end{align} \notag $$

    $$ \begin{align} r^{'}_{e} &= \frac{26\ mV}{I_E} \notag \\   r^{'}_{e} &= \frac{26\ mV}{365\ μA}  \notag \\ r^{'}_{e} &= 71.2\ Ω \notag\end{align} \notag $$

     

    For the single ended output gain,

    $$ A_v = \frac{r_c}{2(r^{'}_{e}+r_{E})} \notag $$

    $$ A_v = \frac{8\ kΩ}{2(71.2\ Ω+30\ Ω)} \notag $$

    $$ A_v = \frac{8\ kΩ}{202.4\ Ω} \notag $$

    $$ A_v = 39.5 \notag $$

    The differential output gain is twice this value, or 79.

     

    Because it is possible to drive a diff amp with two distinct inputs, a wide variety of outputs may be obtained. It is useful to investigate two specific cases:

    • Two identical inputs in both phase and magnitude.
    • Two inputs with identical magnitude, but 180 degrees out of phase.

    Let’s consider the collector potentials for the first case. Assume that a diff amp has a single-ended input/single-ended output gain of 100 and a 10 mV signal is applied to both bases. Using Superposition, we find that the outputs due to each input are 100 times 10 mV, or 1 V in magnitude. For the first input, the voltages are sketched in Figure 1.25a (following page). For the second input, the voltages are sketched in Figure 1.25b. Note that each collector sees both a sine wave and an inverted sine wave, both of equal amplitude. When these two signals are added, the result is zero, as seen in Figure 1.25c. In equation form,

    $$ v_{C1} = v_{in1} (−A_v )+v_{in2}\ A_v \notag $$

    $$ v_{C1} = A_v(v_{in2}−v_{in1}) \notag $$

    Because \(v_{in1}\) and \(v_{in2}\) are identical, the output is ideally zero given a perfectly matched and biased diff amp. The exact same effect is seen on the opposite collector. This last equation is very important. It says that the output voltage is equal to the gain times the difference between the two inputs. This is how the differential amplifier got its name. In this case, the two inputs are identical, and thus their difference is zero. On the other hand, if we were to invert one of the input signals(case 2), we find a completely different result.

    $$ \begin{align} v_{in1} &= -v_{in2} \notag \\  v_{C1} &= A_v(v_{in2}-v_{in1}) \notag \\ v_{C1} &= A_v(v_{in2}-(-v_{in2})) \notag \\ v_{C1} &= 2\ A_v\ v_{in2} \notag\end{align} \notag $$

     

    Thus, if one input is inverted, the net result is a doubling of gain. This effect is shown graphically in Figures 1.25d through 1.25f. In short, a differential amplifier suppresses in phase signals while simultaneously boosting out of phase signals. This can be a very useful attribute, particularly in the area of noise reduction.

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    Common Mode Rejection

    By convention, in phase signals are known as common-mode signals. An ideal differential amplifier will perfectly suppress these common-mode signals, and thus, its common-mode gain is said to be zero. In the real world, a diff amp will never exhibit perfect common-mode rejection. The common-mode gain may be made very small, but it is never zero. For a common-mode gain of zero, the two halves of the circuit have to be perfectly matched, and all circuit elements must be ideal. This is impossible to achieve as errors may arise from several sources. The most obvious error sources are resistor tolerance variations and transistor parameter spreads. The basic design of the circuit will also affect the common-mode gain. With some circuit rearrangements, it is possible to determine a common-mode gain for the circuits we have been using. The circuit of Figure 1.20 has been redrawn in Figure 1.26 in order to emphasize its parallel symmetry.

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    Because the DC potentials are identical in both halves, and identical signals drive both inputs, we can combine resistors in parallel in order to arrive at the circuit of Figure 1.27.

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    Although it is not shown explicitly on the diagram, the internal dynamic resistances \((r^{'}_e\)) may also be combined (\(r^{'}_{e}/2). This circuit has been effectively reduced to a simple common emitter stage. Based on our earlier work, the gain for this circuit is

    $$ A_{v(cm)} = \frac{\frac{r_C}{2}}{R_T + \frac{r^{'}_e}{2} + \frac{r_E}{2}} \notag $$

     

    This is the common-mode voltage gain. If \(R_T\) is considerably larger than \(r_C\), then this circuit will exhibit good common mode rejection (assuming that the other parts are matched, naturally). \(R_T\) is the effective resistance of the tail current source. A very high internal resistance (i.e., an ideal current source) is desirable. There are many ways of creating a more ideal current source. One way is to use a third bipolar transistor as shown in Figure 1.28.

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    The tail current is found by determining the potential across \(R_2\) and subtracting the 0.7 V \(V_{BE}\) drop. The remaining potential appears across \(R_3\). Given the voltage and resistance, Ohm’s Law will let you find the tail current. In this circuit, \(R_2\) is sometimes replaced with a Zener diode. This can help to reduce temperature induced current fluctuations. In any case, the effective resistance of this current source is considerably larger than the simple tail resistor variation. It is largely dependent on the characteristics of the tail current transistor, and can easily be in the megohm region.

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    Current Mirror

    A very popular biasing technique in integrated circuits involves the current mirror. Current mirrors are also employed as active loads in order to optimize a circuit’s gain. A simple current mirror is shown in Figure 1.29. This circuit requires that the transconductance curves of the diode and the transistor be very closely matched. One way to guarantee this is to use two transistors, and form one of them into a diode by shorting its collector to its base. If we use an approximate forward bias potential of 0.7 V and ignore the small base current, the current through the diode is

    $$ I_D= \frac{V_{CC}−0.7\ V}{R} \notag $$

    In reality, the diode potential will probably not be exactly 0.7 V. This will have little effect on \(I_d\) though. Because the diode is in parallel with the transistor’s base-emitter junction, we know that \(V_d=V_{BE}\). If the two devices have identical transconductance curves, the transistor’s emitter current will equal the diode current. You can think of the transistor as mirroring the diode’s current, hence the circuit’s name. If the two device curves are slightly askew, then the two currents will not be identical. This is shown graphically in Figure 1.30.

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    Example 1.20

    A current mirror could be used in the circuit of Figure 1.28. The result is shown in Figure 1.31. If the positive power supply is 15 V, the negative supply is -10 V, and \(R\) is 10 kΩ, the tail current will be

    $$ I_D = \frac{V_{CC} −V_{EE} −V_{D}}{R} \notag $$

    $$ I_D = \frac{15\ V -(-10\ V) -0.7\ V}{10 kΩ} \notag $$

    $$ I_D = 2.43\ mA \notag $$

    Because the tail current is the mirror current,

    $$ I_T = I_D \notag $$

    $$ I_T = 2.43\ mA \notag $$

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    Biasing of this type is very popular in operational amplifiers. Another use for current mirrors is in the application of active loads. Instead of using simple resistors for the collector loads, a current mirror may be used instead. A PNP based current mirror suitable for use as an active load in our previous circuits is shown in Figure 1.32.

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    To use this, we simply remove the two collector resistors from a circuit such as Figure 1.31, and drop in the current mirror. The result of this operation is shown in Figure 1.33. The current mirror active load produces a very high internal impedance, thus contributing to a very high differential gain. In effect, by using a constant current source in the collectors, all AC current is forced into the following stage. You may also note that the number of resistors used in the circuit has decreased considerably.

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    Summary

     

    We have seen how to convert gains and signals into a decibel form for both powers and voltages. This is convenient because what would require multiplication and division under the ordinary scheme only requires simple addition and subtraction in the dB scheme. Along with this, dB measurement is used almost exclusively for Bode gain plots. A Bode plot details a system’s gain magnitude and phase response. For gain, the amplitude is measured in dB, while the frequency is normally presented in log form. For a phase plot, phase is measured in degrees, and again, the frequency axis is logarithmic. The changes in gain and phase at the frequency extremes are caused by lead and lag networks. Lead networks cause the low frequency gain to roll off. The roll off rate is 6 dB per octave per network. The phase will change from +90 degrees to 0 degrees per network. Lag networks cause the high frequency gain to roll off at a rate of -6 dB per octave per network. The phase change per lag network is from 0 degrees to -90 degrees. It was noted that computers may be used to quickly tabulate the response of complex networks such as these. Many computer circuit simulators are based on the original SPICE program. Among the popular commercial simulation programs are PSpice and Multisim. Freeware versions include LTspice and TINA-TI. Packages such as these offer graphical schematic capture tools and large component libraries. Differential amplifiers are symmetrical circuits, employing a minimum of two active devices. They may be configured with single or dual inputs, and single or dual outputs. Diff amps are commonly used as the first stage of an operational amplifier. They tend to amplify the difference in the input signals while simultaneously suppressing in-phase, or common-mode, signals. Current mirrors are widely used for biasing purposes and as active loads. Active loads offer the advantage of producing higher gains than ordinary resistive loads.

     

    Review Questions

    1. What are the advantages of using decibels over the ordinary scheme?
    2. How do decibel power and voltage gain calculations differ?
    3. What does the third letter in a decibel-based signal measurement indicate (as in dBV or dBm)?
    4. What is a Bode plot?
    5. What is a lead network? What general response does it yield?
    6. What is a lag network? What general response does it yield?
    7. What do the terms \(f_1\) and \(f_2\) indicate about a system’s response?
    8. What are the rolloff slopes for lead and lag networks?
    9. What are the phase changes produced by individual lead and lag networks?
    10. How is risetime related to upper break frequency?
    11. How do multiple lead or lag networks interact to form an overall system response?
    12. What is SPICE?
    13. What is common-mode rejection?
    14. What is a current mirror?
    15. What is the advantage of using an active load?

     

    Problems

     

    Analysis Problems - dB emphasis

    1. Convert the following power gains into dB form: a) 10 b) 80 c) 500 d) 1 e) 0.2 f) 0.03.
    2. Convert the following dB power gains into ordinary form: a) 0 dB b) 12 dB c) 33.1 dB d) 0.2 dB e) -5.4 dB f) -20 dB.
    3. An amplifier has an input signal of 1 mW, and produces a 2 W output. What is the power gain in dB?
    4. A Hi-Fi power amplifier has a maximum output of 50 W and a power gain of 19 dB. What is the maximum input signal power?
    5. An amplifier with a power gain of 27 dB is driven by a 25 mW source. Assuming the amplifier doesn’t clip, what is the output signal in Watts?
    6. Convert the following voltage gains into dB form: a) 10 b) 40 c) 250 d) 1 e) 0.5 f) 0.004
    7. Convert the following dB voltage gains into ordinary form: a) 0.5 dB b) 0 dB c) 46 dB d) 10.7 dB e) -8 dB f) -14.5 dB
    8. A guitar pre-amp has a gain of 44 dB. If the input signal is 12 mV, what is the output signal?
    9. A video amplifier has a 140 mV input and a 1.2 V output. What is the voltage gain in dB?
    10. The pre-amp in a particular tape deck can output a maximum signal of 4 V. If this amplifier has a gain of 18 dB, what is the maximum input signal?
    11. Convert the following powers into dBW: a) 1 W b) 23 W c) 6.5 W d) 0.2W e) 2.3 mW f) 1.2 kW g) 0.045 mW h) 0.3 μW i) 5.6E-18 W.
    12. Repeat Problem 11 for units of dBm.
    13. Repeat Problem 11 for units of dBf.
    14. Convert the following voltages into dBV: a) 12.4 V b) 1 V c) 0.25 V d) 1.414 V e) 0.1 V f) 10.6 kV g) 13 mV h) 2.78 μV.
    15. A two stage power amplifier has power gains of 12 dB and 16 dB. What is the total gain in dB and in ordinary form?
    16. If the amplifier of Problem 15 has an input of -18 dBW, what is the final output in dBW? in dBm? in Watts?
    17. Referring to Figure 1.1, what are the various stages’ outputs if the input is changed to -4 dBm? to -34 dBW?
    18. Which amplifier has the greatest power output? a) 50 Watts b) 18 dBW c) 50 dBm.
    19. Which amplifier has the greatest power output? a) 200 mW b) -10 dBW c) 22 dBm
    20. A three stage amplifier has voltage gains of 20 dB, 5 dB, and 12 dB respectively. What is the total voltage gain in dB and in ordinary form?
    21. If the circuit of Problem 20 has an input voltage of -16 dBV, what are the outputs of the various stages in dBV? In volts?
    22. Repeat Problem 21 for an input of 12 mV
    23. Which amplifier produces the largest output voltage? a) 15 V b) 16 dBV

    Analysis Problems - Bode plot emphasis

     

    24. Given a lead network critical at 3 kHz, what are the gain and phase values at 100 Hz, 3 kHz, and 40 kHz?

    25. Given a lag network tuned to 700 kHz, what are the gain and phase values at 50 kHz, 700 kHz, and 10 MHz? What is the risetime?

    26. A noninverting amplifier has a midband voltage gain of 18 dB and a single lag network at 200 kHz. What are the gain and phase values at 30 kHz, 200 kHz, and 1 MHz. What is the risetime?

    27. Repeat Problem 26 for an inverting (-180 degrees) amplifier.

    28. Draw the Bode plot for the circuit of Problem 26.

    29. Draw the Bode plot for the circuit of Problem 27.

    30. An inverting (-180 degrees) amplifier has a midband gain of 32 dB and a single lead network critical at 20 Hz (assume the lag network \(f_c\) is high enough to ignore for low frequency calculations). What are the gain and phase values at 4 Hz, 20Hz, and 100 Hz?

    31. Repeat Problem 29 with a noninverting amplifier.

    32. Draw the Bode plot for the circuit of Problem 30.

    33. Draw the Bode plot for the circuit of Problem 31.

    34. A noninverting amplifier used for ultrasonic applications has a midband gain of 41 dB, a lag network critical at 250 kHz, and a lead network critical at 30 kHz. Draw its gain Bode plot.

    35. Find the gain and phase at 20 kHz, 100 kHz, and 800 kHz for the circuit of Problem 34.

    36. If the circuit of Problem 34 has a second lag network added at 300 kHz, What are the new gain and phase values at 20 kHz, 100 kHz, and 800 kHz?

    37. Draw the gain Bode plot for the circuit of Problem 36.

    38. What are the maximum and minimum phase shifts across the entire frequency spectrum for the circuit of Problem 36?

    39. A noninverting DC amplifier has a midband gain of 36 dB, and lag networks at 100 kHz, 750 kHz, and 1.2 MHz. Draw its gain Bode plot.

    40. What are the maximum and minimum phase shifts across the entire frequency spectrum for the circuit of Problem 39?

    41. What is the maximum rate of high frequency attenuation for the circuit of Problem 39 in dB/Decade?

    42. If an amplifier has two lead networks, what is the maximum rate of low frequency attenuation in dB/Octave?

     

    Analysis Problems - Differential amplifier emphasis

     

    43. Given the circuit of Figure 1.20, determine the single-ended input/singleended output gain for the following values: \(R_B=5 kΩ\) , \(R_T=7.5 kΩ\), \(R_C=12 kΩ\) , \(V_{CC} =25 V\), \(V_{EE}=-9 V\), \(r_E=50 Ω\)

    44. Determine the differential voltage gain in the circuit of Figure 1.28 if \(R_B= 15 kΩ\), \(R_1=5 kΩ\), \(R_2=7 kΩ\), \(R_3= 10 kΩ\), \(R_C= 20 kΩ\), \(V_{CC}= 22 V\), \(V_{EE}=-12 V\), \(r_E=75 Ω\).

    45. For the circuit of Problem 44, determine the output at collector 2 if \(V_{in1}(t)=0.001\ sin 2π1000t\) and \(V_{in2}(t)=-0.001 sin 2π1000t\).

    46. Determine the differential voltage gain in the circuit of Figure 1.31 if \(R_b=8 kΩ\), \(R_{mirror}=22 kΩ\), \(R_C=10 kΩ\), \(V_{CC}=18 V\), \(V_{EE}=-15 V\), \(r_E=25 Ω\).

    47. For the circuit of Problem 46, determine the output at collector 1 if \(V_{in1}(t)=-0.005 sin 2π2000t\) and \(V_{in2}(t)=0.005 sin 2π2000t\).

    48. Determine the tail and emitter currents in the circuit of Figure 1.33 if \(R_B=6 kΩ\), \(R_{mirror}=50 kΩ\), \(V_{CC}=15 V\), \(V_{EE}=-15 V\), \(r_E=0Ω\).

     

    Challenge Problems

     

    49. You would like to use a voltmeter to take dBm readings in a 600 Ω system. What voltage should produce 0 dBm?

    50. Assuming that it takes about an 8 dB increase in sound pressure level in order to produce a sound that is subjectively “twice as loud” to the human ear, can a Hi-Fi using a 100 W amplifier sound twice as loud as one with a 40 W amplifier (assuming the same loudspeakers)?

    51. Hi-Fi amplifiers are often rated with a “headroom factor” in dB. This indicates how much extra power the amplifier can produce for short periods of time, over and above its nominal rating. What is the maximum output power of a 250 W amplifier with 1.6 dB headroom?

    52. If the amplifier of Problem 34 picks up an extraneous signal that is a -10 dBV sine wave at 15 kHz, what is the output?

    53. If the amplifier of Problem 39 picks up a high frequency interference signal at 30 MHz, how much is it attenuated over a normal signal? If this input signal is measured at 2 dBV, what should the output be?

    54. If an amplifier has two lag networks, and both are critical at 2 MHz, is the resulting \(f_2\) less than, equal to, or greater than 2 MHz?

    55. If an amplifier has two lead networks, and both are critical at 30 Hz, is the resulting \(f_1\) less than, equal to, or greater than 30 Hz?

     

    Computer Simulation Problems

     

    56. Use a simulator to plot the Bode gain response of the circuit in Problem 39.

    57. Use a simulator to plot the Bode phase response of the circuit in Problem 34.

    58. Use a simulation program to generate a Bode plot for a lead network comprised of a 1 kΩ resistor and a 100 nF capacitor.