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10.2: JFET Internals

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    A simplified internal model of a JFET is shown in Figure \(\PageIndex{1}\). The main portion of the device is called the channel. The diagram illustrates an N-channel device. The channel is built upon a substrate (i.e., base layer) of oppositely doped material. Attached to the opposing ends of the channel are two terminals; the source and the drain. Embedded within the channel is a region using the opposite material type. A lead is attached to this as well and is called the gate. Although there is not perfect correspondence between them, the drain, source and gate are roughly analogous to the BJT's collector, emitter and base, respectively.


    Figure \(\PageIndex{1}\): Simplified internal structure of an N-channel JFET.

    This diagram is drawn symmetrically. Some devices are designed in this fashion and their drain and source terminals can be swapped with no change in operation. This is not true for all devices, though. For small values of drain-source voltage, the channel exhibits a certain amount of resistance that is dependent on the doping level and physical layout of the device. Further, under normal operation, \(I_D\) will equal \(I_S\).

    To understand how the device behaves, refer to Figure \(\PageIndex{2}\). Here we shall consider electron flow (shown as a dashed line). First, a positive voltage, \(V_{DD}\), is attached to the drain terminal along with a current limiting resistor, \(R_D\). A negative supply, \(V_{GG}\), is applied to the gate terminal via resistor \(R_G\). Let's start with the gate supply set to zero. If we start \(V_{DD}\) at zero, here is what happens as we increase its value. Initially, an increase in drain-source voltage will elicit a proportional increase in the current flowing through the channel. In other words, the channel acts like a resistor. As the voltage across the drain-source increases further, at some point the current will saturate, and no further increases in current will occur in spite of further increases in \(V_{DD}\) and \(V_{DS}\). At this point the device is behaving as a constant current source. The drain-source voltage where this transition occurs is called the pinch-off voltage, \(V_p\). If the drain-source voltage increases too much, breakdown will occur and current will begin to increase rapidly.

    What's particularly interesting is what happens when the gate supply is increased in the negative direction. This reverse-biases the gate-source PN junction and results in a larger depletion region being formed. The depletion region widens into the channel, thus restricting current flow sooner and at a lower level. The more negative we make \(V_{GG}\), the lower \(I_D\) becomes. Eventually, when \(V_{GG}\) goes negative enough, the drain current will turn off. This voltage is called \(V_{GS(off)}\) and it has the same magnitude as \(V_P\) (i.e., \(V_P = |V_{GS(off)}|)\). The action can be thought of as operating like a water valve: turning the gate source voltage more negative is like turning off the spigot and decreasing the flow.


    Figure \(\PageIndex{2}\): Electron flow in an N-channel JFET.

    The operation of the JFET can visualized nicely by plotting a set of drain curves, as shown in Figure \(\PageIndex{3}\).


    Figure \(\PageIndex{3}\): JFET drain curves.

    The drain curve family plots drain current, \(I_D\), versus drain-source voltage, \(V_{DS}\). We begin with the top-most curve. This is generated by setting the gate-source voltage, \(V_{GS}\), to zero. We then cycle \(V_{DS}\) from zero to some higher value. Initially, we see a proportional rise in \(I_D\) as \(V_{DS}\) increases. This is called the ohmic or triode region. Eventually, the channel saturates and the current levels out. This is the constant current or saturation region and it occurs for \(V_{DS} > V_P\). The breakdown voltage is called \(BV_{DGS}\), or alternately, \(V_{(BR)DS}\). Above this voltage the current increases rapidly. As usual, we do not wish to operate the device in this breakdown region.

    If we now repeat the process but this time use a small negative value for \(V_{GS}\), we will trace out a curve of very similar shape. The transition to constant current mode will happen at a slightly lower voltage and the current value will be somewhat lower as well. This process continues in like fashion as we make \(V_{GS}\) more and more negative. Eventually, when \(V_{GS} = V_{GS(off)}\), the drain current drops to virtually zero (in fact, a small leakage current flows called \(I_{D(off)}\)). In contrast, if \(V_{GS}\) was allowed to go positive, operation would be lost because the PN junction would become forward-biased and we would lose control of the current via the depletion region. This means that the JFET's current control is entirely in the second quadrant and the largest drain current flows when \(V_{GS} = 0\) V. This current is called \(I_{DSS}\), which stands for the drain current with a shorted gate-source (i.e, if it's shorted, then \(V_{GS} = 0\) V). The JFET cannot produce a continuous current larger than \(I_{DSS}\) safely.

    The characteristic equation relating drain current and gate-source voltage is shown below. This is valid for the constant current region (i.e., \(V_{DS} > V_P\)).

    \[I_D = I_{DSS} \left( 1 − \frac{V_{GS}}{V_{GS (off )}} \right)^2 \label{10.1} \]


    \(V_{GS}\) is the gate-source voltage (\(V_{GS(off)} \leq V_{GS} \leq 0\)),

    \(I_D\) is the drain current,

    \(I_{DSS}\) is the maximum current,

    \(V_{GS(off)}\) is the turn-off voltage.

    From this we see that the JFET is a square-law device rather than like the BJT which has a logarithmic characteristic.1 In essence, this curve is a portion of a parabola. This means that the JFET's characteristic curve is much more gradual in slope than that of a BJT. This will have important implications when it comes to voltage gain potential and distortion, as we shall see in the following chapter.

    It is useful to remember that \(V_{GS(off)}\) and \(I_{DSS}\) are unique to a given device, rather like \(\beta\) is for a BJT. There can also be a fairly large variation in these parameters. For example, a particular model of JFET might show an \(I_{DSS}\) variation between 2 mA and 20 mA, and a \(V_{GS(off)}\) variation between −2 V and −8 V. Generally, the most negative \(V_{GS(off)}\) values will be associated with the largest \(I_{DSS}\) values.

    Equation \ref{10.1} is plotted in Figure \(\PageIndex{4}\). Compare this curve to the curve generated by the Shockley equation for BJTs, Figure 7.2.1. The graph is shown in normalized form. Instead of plotting for specific values of \(V_{GS(off)}\) and \(I_{DSS}\), the axes are presented as fractional portions of the maximums (i.e., the horizontal axis is \(−V_{GS}/V_{GS(off)}\) and the vertical axis is \(I_D/I_{DSS}\)).


    Figure \(\PageIndex{4}\): JFET normalized characteristic curve (note: this uses \(-V_{GS}/V_{GS(off)}\) for the normalized voltage so that the curve does not appear reversed compared to a typical device curve).

    Example \(\PageIndex{1}\)

    Using both Equation \ref{10.1} and the graph of Figure \(\PageIndex{4}\), determine the drain current if the gate-source voltage is −1 V and the JFET specs are \(I_{DSS}\) = 8 mA and \(V_{GS(off)}\) = −2 V.

    First, using Equation \ref{10.1}

    \[I_D = I_{DSS} \left( 1 − \frac{V_{GS}}{V_{GS (off )}} \right)^2 \nonumber \]

    \[I_D = 8mA \left( 1 − \frac{−1V}{−2V} \right)^2 \nonumber \]

    \[I_D = 2 mA \nonumber \]

    Using the graph, \(V_{GS}/V_{GS(off)}\) is 1 V/−2 V, or −0.5. Find this value on the horizontal axis, follow up to the curve and then across to the right vertical axis. The normalized drain current is 0.25, thus \(I_D\) is 0.25 \(I_{DSS}\), or 2 mA.

    As the characteristic curve plots output current versus input voltage, the slope of this represents the transconductance, an important characteristic for biasing and signal analysis. Device transconductance is denoted as \(g_m\), or alternately as \(g_{fs}\), and given units of siemens. We can derive an equation for transconductance by taking the derivative of Equation \ref{10.1}.

    \[I_D = I_{DSS} \left( 1 − \frac{V_{GS}}{V_{GS (off )}} \right)^2 \nonumber \]

    \[\frac{d I_D}{d V_{GS}} =− \frac{2 I_{DSS}}{V_{GS (off )}} \left( 1 − \frac{V_{GS}}{V_{GS (off )}} \right) \nonumber \]

    The coefficient \(−2 I_{DSS}/V_{GS(off)}\) is defined as \(g_{m0}\), the transconductance when \(V_{GS} = 0\) V. This is the maximum transconductance of the device. Substituting, we arrive at

    \[g_{m0} =− \frac{2 I_{DSS}}{V_{GS(off )}} \label{10.2} \]

    \[g_m = g_{m0} \left( 1 − \frac{V_{GS}}{V_{GS (off )}} \right) \label{10.3} \]

    A normalized plot of transconductance versus \(V_{GS}\) is shown in Figure \(\PageIndex{5}\). The horizontal axis is \(−V_{GS}/V_{GS(off)}\) and the vertical axis is \(g_m/g_{m0}\).


    Figure \(\PageIndex{5}\): Curve of transconductance.

    From this graph we see that the transconductance is a linear function.

    Another item of interest regarding these device equations: If we combine Equations \ref{10.1} and \ref{10.3}, we generate two equations that will prove useful in upcoming work.

    \[\frac{g_m}{g_{m0}} = \sqrt{\frac{I_D}{I_{DSS}}} \label{10.4} \]

    \[\frac{I_D}{I_{DSS}} = \left( \frac{g_m}{g_{m0}} \right)^2 \label{10.5} \]

    Before moving on, the schematic symbols for JFETs are shown in Figure \(\PageIndex{6}\). The middle vertical line represents the channel, and as is usually the case, the arrow points to N material. Sometimes the gate arrow is draw in the middle rather than toward the source. Also, as is the case the BJT, sometimes these symbols are drawn within a circle.


    Figure \(\PageIndex{6}\): JFET schematic symbols: N-Channel (left) P-Channel (right)


    1As evidenced in the Shockley equation, Equation 2.1.1.

    This page titled 10.2: JFET Internals is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by James M. Fiore via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.