3: Caching
- Page ID
- 123267
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\(\newcommand{\avec}{\mathbf a}\) \(\newcommand{\bvec}{\mathbf b}\) \(\newcommand{\cvec}{\mathbf c}\) \(\newcommand{\dvec}{\mathbf d}\) \(\newcommand{\dtil}{\widetilde{\mathbf d}}\) \(\newcommand{\evec}{\mathbf e}\) \(\newcommand{\fvec}{\mathbf f}\) \(\newcommand{\nvec}{\mathbf n}\) \(\newcommand{\pvec}{\mathbf p}\) \(\newcommand{\qvec}{\mathbf q}\) \(\newcommand{\svec}{\mathbf s}\) \(\newcommand{\tvec}{\mathbf t}\) \(\newcommand{\uvec}{\mathbf u}\) \(\newcommand{\vvec}{\mathbf v}\) \(\newcommand{\wvec}{\mathbf w}\) \(\newcommand{\xvec}{\mathbf x}\) \(\newcommand{\yvec}{\mathbf y}\) \(\newcommand{\zvec}{\mathbf z}\) \(\newcommand{\rvec}{\mathbf r}\) \(\newcommand{\mvec}{\mathbf m}\) \(\newcommand{\zerovec}{\mathbf 0}\) \(\newcommand{\onevec}{\mathbf 1}\) \(\newcommand{\real}{\mathbb R}\) \(\newcommand{\twovec}[2]{\left[\begin{array}{r}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\ctwovec}[2]{\left[\begin{array}{c}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\threevec}[3]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\cthreevec}[3]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\fourvec}[4]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\cfourvec}[4]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\fivevec}[5]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\cfivevec}[5]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\mattwo}[4]{\left[\begin{array}{rr}#1 \amp #2 \\ #3 \amp #4 \\ \end{array}\right]}\) \(\newcommand{\laspan}[1]{\text{Span}\{#1\}}\) \(\newcommand{\bcal}{\cal B}\) \(\newcommand{\ccal}{\cal C}\) \(\newcommand{\scal}{\cal S}\) \(\newcommand{\wcal}{\cal W}\) \(\newcommand{\ecal}{\cal E}\) \(\newcommand{\coords}[2]{\left\{#1\right\}_{#2}}\) \(\newcommand{\gray}[1]{\color{gray}{#1}}\) \(\newcommand{\lgray}[1]{\color{lightgray}{#1}}\) \(\newcommand{\rank}{\operatorname{rank}}\) \(\newcommand{\row}{\text{Row}}\) \(\newcommand{\col}{\text{Col}}\) \(\renewcommand{\row}{\text{Row}}\) \(\newcommand{\nul}{\text{Nul}}\) \(\newcommand{\var}{\text{Var}}\) \(\newcommand{\corr}{\text{corr}}\) \(\newcommand{\len}[1]{\left|#1\right|}\) \(\newcommand{\bbar}{\overline{\bvec}}\) \(\newcommand{\bhat}{\widehat{\bvec}}\) \(\newcommand{\bperp}{\bvec^\perp}\) \(\newcommand{\xhat}{\widehat{\xvec}}\) \(\newcommand{\vhat}{\widehat{\vvec}}\) \(\newcommand{\uhat}{\widehat{\uvec}}\) \(\newcommand{\what}{\widehat{\wvec}}\) \(\newcommand{\Sighat}{\widehat{\Sigma}}\) \(\newcommand{\lt}{<}\) \(\newcommand{\gt}{>}\) \(\newcommand{\amp}{&}\) \(\definecolor{fillinmathshade}{gray}{0.9}\)- 3.1: How programs run
- This page explains how programs are executed in computers, emphasizing the significance of caching to mitigate memory bottlenecks. It outlines the loading of programs from storage into memory and the function of CPU registers, including the program counter and instruction register. The instruction cycle is detailed, including the stages of fetching, decoding, and executing instructions categorized into load, arithmetic/logic, store, and jump/branch operations.
- 3.2: Cache performance
- This page explains caching as a performance enhancement for CPUs, utilizing fast, small memory to store frequently accessed values. It outlines the different cache levels (L1, L2, L3), with L1 being the fastest. Caches can fill up, requiring older data to be replaced, which may cause cache misses that slow processing.
- 3.3: Locality
- This page explains cache memory operation, emphasizing temporal and spatial locality. It describes how loading a block of neighboring data upon reading a byte enhances access speed and indicates that sequential execution, loops, and arrays improve cache efficiency. While predictable data access yields high hit rates, unpredictable access can result in poor performance.
- 3.4: Measuring cache performance
- This page describes a U.C. Berkeley Computer Architecture programming exercise that evaluates average read/write times in an array to analyze cache characteristics. The program employs dual loops for accessing and incrementing, aiding in calculating average miss penalties.
- 3.5: Programming for cache performance
- This page discusses memory caching and its performance benefits for programmers. It highlights strategies to improve cache efficiency, such as single-pass array traversal and optimized access patterns. It notes the challenges with linked data structures regarding spatial locality and mentions that recursive algorithms, like mergesort, can enhance cache behavior.
- 3.6: The memory hierarchy
- This page discusses the differences between caches and DRAM in terms of speed, size, and cost, highlighting that smaller caches are faster but more expensive, while larger caches are slower and more reliant on main memory. It outlines a memory hierarchy that includes various storage types (registers, caches, DRAM, SSDs, HDDs, and tape drives) that serve different roles based on access time, size, and cost, demonstrating the trade-offs that define efficient memory utilization.
- 3.7: Caching policy
- This page discusses the memory hierarchy framework, focusing on caching management, data movement, timing, and cache placement. It highlights the varying data management from compilers and CPUs to administrators, with block sizes growing down the hierarchy. Basic caches operate on first use, while many employ prefetching.
- 3.8: Paging
- This page explains virtual memory and paging in operating systems, detailing how processes allocate memory by transferring data between physical memory and disk storage. The OS manages memory requests by granting space or swapping pages, optimizing usage but potentially causing delays due to thrashing when excessive processes compete for memory. Although thrashing is theoretically avoidable, many systems lack effective management techniques, often putting the onus on users to manage memory use.