9.5.7: Integrated Circuit Well and Gate Creation

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We then remove the remaining resist, and perform an activation/anneal/diffusion step, also sometimes called the "drive-in". The purpose of this step is twofold. We want to make the n-tank deep enough so that we can use it for our p-channel MOS, and we want to build up an implant barrier so that we can implant into the p-substrate region only. We introduce oxygen into the reactor during the activation, so that we grow a thicker oxide over the region where we implanted the phosphorus. The nitride layer over the p-substrate on the LHS protects that area from any oxide growth. We then end up with the structure shown in Figure \(\PageIndex{1}\).

As shown in Figure 7 from the previous section, most of the silicon layer is p-type but a portion of the layer, on the top right, is now n-type. Due to the anneal and drive-in process, a new oxide layer has been grown over the right half of the silicon. As the oxide layer expands beyond the edge of the nitride layer on the left half of the assembly, it increases significantly in height. — Figure \(\PageIndex{1}\): After the Anneal/Drive-In

Now we strip the remaining nitride. Since the only way we can convert from p to n is to add a donor concentration which is greater than the background acceptor concentration, we had to keep the doping in the substrate fairly light in order to be able to make the n-tank. The lightly doped p-substrate would have too low a threshold voltage for good n-MOS transistor operation, so we will do a \(V_{T}\) adjust implant through the thin oxide on the left hand side, with the thick oxide on the right side blocking the boron from getting into the n-tank. This is shown in Figure \(\PageIndex{2}\), where boron is implanted into the p-type substrate on the left side, but is blocked by the thick oxide in the region over the n-well.

Boron atoms move downwards onto the wafer from Figure 1 above. They penetrate into the p-type silicon on the left side of the assembly, where the oxide layer is thin, but are blocked from entering the region of the n-type silicon due to the much thicker oxide layer present over this region. — Figure \(\PageIndex{2}\): \(V_{T}\) adjust implant

Next, we strip off all the oxide and grow a new thin layer of oxide, and then a layer of nitride (Figure \(\PageIndex{3}\)). The oxide layer is grown only because it is bad to grow \(\mathrm{Si}_{3} \mathrm{N}_{4}\) directly on top of silicon, as the different coefficients of thermal expansion between the two materials causes damage to the silicon crystal structure. Also, it turns out to be nearly impossible to remove nitride if it is deposited directly on to silicon.

The p-type silicon block and n-type silicon region from the wafer in Figure 2 above are shown, with a thin layer of sacrificial oxide grown on top of the assembly and a thin layer of nitride grown on top of that. — Figure \(\PageIndex{3}\): Strip oxide, grow new nitride

The nitride is patterned (covered with photoresist, exposed, developed, etched, and cleaned of photoresist) to make two areas which are called "active" (Figure \(\PageIndex{4}\)). (This is where we will build our transistors.) The wafer is then subjected to a high-pressure oxidation step which grows a thick oxide wherever the nitride was removed. The nitride is a good barrier for oxygen, so essentially no oxide grows underneath it. The thick oxide is used to isolate individual transistors, and also to make for an insulating layer over which conducting patterns can be run. The thick oxide is called field oxide (or FOX for short), as shown in Figure \(\PageIndex{5}\).

Three portions of the nitride layer from Figure 3 above are removed: the left edge, which is at the outer edge of the p-type silicon; a central section spanning both the p-type and n-type regions; and the right edge, which is at the outer edge of the n-type silicon. The remaining sections of nitride will define the edges of "active" regions. — Figure \(\PageIndex{4}\): Nitride layer after etching

Field oxide is grown in the active regions from Figure 4 above, penetrating some of the underlying silicon layer and rising some distance above the nitride layer. — Figure \(\PageIndex{5}\): Growing field oxide

Then, the nitride and some of the oxide are etched off. The oxide is etched enough so that all of the oxide under the nitride regions is removed, which will take a little off the field oxide as well. This is because we now want to grow the gate oxide, which must be very clean and pure (Figure \(\PageIndex{6}\). The oxide under the nitride is sometimes called sacrificial oxide, because it is sacrificed in the name of ultra performance.

The assembly from Figure 5 above has all of the nitride layer removed, as well as the regions of the oxide layer that are not directly under the FOX regions.

Then the gate oxide is grown, and immediately thereafter, the whole wafer is covered with polysilicon (Figure \(\PageIndex{7}\)).

A thin layer of gate oxide is grown on the regions of exposed silicon from Figure 6 above, in between the regions of FOX. A thin layer of polysilicon is grown over this entire assembly. — Figure \(\PageIndex{7}\): Poly deposition over gate oxide

The polysilicon is then patterned to form the two regions which will be our gates. The wafer is covered once again with photoresist. The resist is removed over the region that will be the n-channel device, but is left covering the p-channel device. A little area near the edge of the n-tank is also uncovered (Figure \(\PageIndex{8}\)). This will allow us to add some additional phosphorus into the n-well, so that we can make a contact there, so that the n-well can be connected to \(V_{\text{dd}}\).

Most of the gate oxide layer from Figure 7 above is removed, except for a small "gate region" in the middle of each non-FOX region. A layer of photoresist covers most of the n-type silicon region, from the center of the central FOX region to slightly to the left of the rightmost FOX region. — Figure \(\PageIndex{8}\): Preparing for NMOS channel/drain implant

Back into the implanter we go, this time exposing the wafer to phosphorus. The poly gate, the FOX and the photoresist all block phosphorus from getting into the wafer, so we make two n-type regions in the p-type substrate, and we have made our n-channel MOS source/drain regions. We also add phosphorous to the \(V_{\text{dd}}\) contact region in the n-well so as the make sure we get good contact performance there (Figure \(\PageIndex{9}\)).

Phosphorus is shot downwards onto the assembly from Figure 8 above, being blocked from penetrating the silicon in regions covered by FOX or photoresist. In the p-type silicon, this creates a source to the left of the gate and a drain to the right of the gate. A contact in the n-type silicon well is created in the gap between the photoresist and the rightmost FOX region. — Figure \(\PageIndex{9}\): Phosphorus source/drain implant

Note that the formation of the source and drain were performed with a self-aligning technology. This means that we used the gate structure itself to define where the two inside edges of the source and drain would be for the MOSFET. If we had made the source/drain regions before we defined the gate, and then tried to line the gate up right over the space between them, we might have gotten something that looks like what is shown in Figure \(\PageIndex{10}\).

Misaligned gate, with the gate's left edge overlapping the source and its right edge not quite reaching the left edge of the drain. — Figure \(\PageIndex{10}\): Misaligned gate

What's going to be the problem with this transistor? Obviously, if the gate does not extend all the way to both the source and the drain, then the channel will not either, and the transistor will never turn on! We could try making the gate wider, to ensure that it will overlap both active areas, even if it is slightly misaligned, but then you get a lot of extraneous fringing capacitance which will significantly slow down the speed of operation of the transistor (Figure \(\PageIndex{11}\)). This is bad! The development of the self-aligned gate technique was one of the big breakthroughs which has propelled us into the VLSI and ULSI era.

Overly wide gate, with the gate covering sections of both the source and the drain. — Figure \(\PageIndex{11}\): Wide gate

We pull the wafer out of the implanter, and strip off the photoresist. This is sometimes difficult, because the act of ion implantation can "bake" the photoresist into a very tough film. Sometimes an rf discharge in an \(\mathrm{O}_{2}\) atmosphere is used to "ash" the photoresist, and literally burn it off the wafer! We now apply some more PR, and this time pattern to have the moat area, and a substrate contact exposed, for a boron p+ implant. This is shown in Figure \(\PageIndex{12}\).

The wafer from Figure 9 above has its photoresist layer over the n-well removed, and a new photoresist layer placed over the p-type silicon region from the center of the central FOX region to just to the right of the leftmost FOX region. Another photoresist layer covers the rightmost FOX region and the V_dd contact region in the n-well. Boron is shot downwards onto the assembly and blocked by the photoresist, creating a drain to the left of the n-well gate, a source on the right of the n-well gate, and a contact in the p-type silicon just to the left of the photoresist layer there. — Figure \(\PageIndex{12}\): Boron p-Channel S/D Implant

We are almost done. The next thing we do is remove all the photoresist, and grow one more layer of oxide, which covers everything, as shown in Figure \(\PageIndex{13}\). We put photoresist over the whole wafer again, and pattern for contact holes to go through the oxide. We will put contacts for the two drains, and for each of the sources, make sure that the holes are big enough to also allow us to connect the source contact to either the p-substrate or the n-moat as is appropriate (Figure \(\PageIndex{14}\)).