8.3: Conditional Execution and the apsr Register

ARM assembly implements conditional execution of assembly language statements, which allows the results of the previous statement to be used to determine whether or not to execute the current statement. This condition can be applied to any operator, but is most useful for the branch (B and BL) operators. A new operator, the compare (CMP) operator, can be used to compare two registers; the branch taken depends on the conditional execution value set for the instruction. For example, to branch to the label “branchTarget” if r0 = r1, the programmer can use the following code fragment:

    CMP r0, r1 
    BEQ branchTarget

To branch and link (BL) to the function func1 if the value of r0 > r1, the programmer can use the following code fragment:

    CMP r0, r1 
    BLGT func1

The check for the previous statement can be applied to any statement, not just the CMP statement. The following example shows how an S can be appended to the SUB operation, creating a SUBS operation. This operation tells the CPU to store condition flags to categorize the result from this instruction. These condition flags are saved in the Application Program Status Register (apsr).

For example, assume that r4 = r2*(r0-r1), but the code only runs if the value of r0 – r1 is greater than 0.

if ((r0 = r0 – r1) > 0){ 
    r4 = r2 * r0 
}

This can be written in ARM assembly as:

    SUBS r0, r0, r1 
    MULPL r4, r4, r0

In this case if r0 - r1 is positive (PL means plus), the value in r2 will be multiplied with r0 and stored in r4, otherwise the statement is just ignored.

The apsr is a 32-bit register that contains 4 bits that give information about the previous instruction. The 4 bits are condition flags with the following values:

• N – The negative flag, which is set to 1 if the result is negative. This is accomplished by assuming the number is a 2’s complement value and copying the sign bit from the result of the operation.
• Z – The zero flag, which contains 1 to indicate that the result of the instruction is zero.
• C – Carry or Unsigned Overflow, which contains 1 to indicate that the result of the operation the 32-bit result register. This bit can be used to implement 64-bit unsigned arithmetic, for example.
• V – Signed Overflow, which contains the value of 1 if the result of the operation would overflow a signed 32-bit value. For example, 0x7fffffff is the largest positive two's complement integer that can be represented in 32 bits, so 0x7fffffff + 0x7fffffff triggers a signed overflow, but not an unsigned overflow (or carry): the result, 0xfffffffe, is correct if interpreted as an unsigned quantity, but represents a negative value (-2) if interpreted as a signed quantity.

The condition flags set by the SUBS instruction are then checked by the next instruction, the MULPL instruction. The instruction MULPL is a MUL instruction with a condition code PL. The condition code PL means only run the statement if the result from the previous command is positive (PL is short for plus). Thus, the pseudo code above is implemented in the two assembly instructions.

Most ARM assembly operations can have a condition code to indicate whether the instruction should be run or not. For example, saying addgt means to run the add operation if the condition flags indicate the previous instruction resulted in a gt condition, and lslne runs the lsl operation if the previous instruction resulted in a ne condition. This leads to ARM having a dauntingly large number of apparent operations because of the combinations of operations and condition codes, but in reality, the number of actual operations and condition codes is much smaller and manageable.

While having the ability of any assembly language statement to set the condition flags, there are 4 ARM assembly instructions that are specifically associated with setting these flags. These 4 instructions are CMP, CMN, TST, and TEQ. These operands are summarized in the following table.

Operator	Meaning
CMP	Compares the two register operands. The operator is effectively a SUBS but the result is not stored.
CMN	The operator is effectively an ADDS but does not store the result.
TST	The operator is effectively an ANDS but does not store the result. Can be used for bit masking
TEQ	The operator is effectively an EORS but does not store the result. Can be used for bit masking.

Table 11: Assembly instructions that set the condition flags

The format for these operators is summarized below. Examples of how to use the CMP operator will be given later in the chapter.

CMP Rn, Operand2 
CMN Rn, Operand2 
TST Rn, Operand2 
TEQ Rn, Operand2

The condition codes that can be appended to the operators in ARM are summarized in the following table. Note that these condition codes are for the CMP operator only. They do not apply to the CMN, TST, or TEQ operators.

Code	Meaning for CMP operator	Flags used	Condition Code
EQ	Equal	Z = 1	0000 (0X00)
NE	Not Equal	Z = 0	0001 (0X01)
CS or HS	Carry bit set, or unsigned higher or same	C = 1	0010 (0X02)
CC or LO	Carry bit clear or unsigned lower	C = 0	0011 (0X03)
MI	Minus or negative	N = 1	0100 (0X04)
PL	Plus or positive	N = 0	0101 (0X05)
VS	V bit set, or signed overflow	V = 1	0110 (0X06)
VC	V bit clear, or no signed overflow	V = 0	0111 (0X07)
HI	Unsigned higher	C = 1 and Z = 0	1000 (0X08)
LS	Unsigned lower or same	C = 0 or Z = 1	1001 (0X09)
GE	Signed greater than or equal	N = V	1010 (0X0a)
LT	Signed less than	N != V	1011 (0X0b)
GT	Signed greater than	Z = 0 and N = V	1100 (0X0c)
LE	Signed less than or equal	N != V or Z = 1	1101 (0X0d)
AL or omitted	Always execute		1110 (0X0e)

Table -12: Condition Codes

These changes to the assembly instructions permit the final parts of the machine code formats to be explained. If the assembly instruction includes an S, the S-bit in the instruction is set to 1. Finally, if the instruction appends a Condition Code, Table 12 above can be used to find the value to set this code to.