Skip to main content
Engineering LibreTexts

21.4: Appendix D - Quiz Question Answers

  1. Last updated
  2. Save as PDF
  • Page ID
    54596

    • \( \newcommand{\vecs}[1]{\overset { \scriptstyle \rightharpoonup} {\mathbf{#1}} } \) \( \newcommand{\vecd}[1]{\overset{-\!-\!\rightharpoonup}{\vphantom{a}\smash {#1}}} \)\(\newcommand{\id}{\mathrm{id}}\) \( \newcommand{\Span}{\mathrm{span}}\) \( \newcommand{\kernel}{\mathrm{null}\,}\) \( \newcommand{\range}{\mathrm{range}\,}\) \( \newcommand{\RealPart}{\mathrm{Re}}\) \( \newcommand{\ImaginaryPart}{\mathrm{Im}}\) \( \newcommand{\Argument}{\mathrm{Arg}}\) \( \newcommand{\norm}[1]{\| #1 \|}\) \( \newcommand{\inner}[2]{\langle #1, #2 \rangle}\) \( \newcommand{\Span}{\mathrm{span}}\) \(\newcommand{\id}{\mathrm{id}}\) \( \newcommand{\Span}{\mathrm{span}}\) \( \newcommand{\kernel}{\mathrm{null}\,}\) \( \newcommand{\range}{\mathrm{range}\,}\) \( \newcommand{\RealPart}{\mathrm{Re}}\) \( \newcommand{\ImaginaryPart}{\mathrm{Im}}\) \( \newcommand{\Argument}{\mathrm{Arg}}\) \( \newcommand{\norm}[1]{\| #1 \|}\) \( \newcommand{\inner}[2]{\langle #1, #2 \rangle}\) \( \newcommand{\Span}{\mathrm{span}}\)\(\newcommand{\AA}{\unicode[.8,0]{x212B}}\)

    This appendix provides answers for the quiz questions in each chapter.

    24.1 Quiz Question Answers, Chapter 1

    There are no quiz questions for Chapter 1.

    24.2 Quiz Question Answers, Chapter 2

    1)  See Section 2.1, Illustration 1, Computer Architecture.

    2)  Bus or Interconnection.

    3)  Secondary storage.

    4)  Primary storage or main memory (RAM).

    5)  Keeps a copy of the data closer to the CPU, eliminating the extra time required to access the RAM via the Bus.

    6)  4 bytes.

    7)  1 byte.

    8)  The LSB is 4016 and the MSB is 0016.

    9)  The answer is as follows:

    截屏2021-08-02 下午2.29.40.png

    10) The layout is:

    截屏2021-08-02 下午2.30.00.png

    11) The answers are as follows:

    1. 8
    2. 64
    3. 16
    4. 32
    5. 64
    6. 8
    7. 8
    8. 16

    12)  The rip register.

    13)  The rsp register.

    14)  The rax register is: \(0000000000000000_{16}\).

    15)  The answers are as follows:

    1. EF\(_{16}\)
    2. CDEF\(_{16}\)
    3. 89ABCDEF\(_{16}\)
    4. 0123456789ABCDEF\(_{16}\)

    24.3 Quiz Question Answers, Chapter 3

    1) The answers are as follows:

    1. -128 to +127

    2. 0 to 255

    1. −32,768 to +32,767

    2. 0 to 65,535

    3. −2,147,483,648 to +2,147,483,647

    4. 0 to 4,294,967,295

    2)  The answers are as follows:

    1. 5
    2. 9
    3. 13
    4. 21

    3)  The answers are as follows:

    1. 0xFD
    2. 0x0B
    3. 0xF7
    4. 0xEB

    4)  The answers are as follows:

    1. 0xFFEF
    2. 0x0011
    3. 0xFFE1
    4. 0xFF76

    5)  The answers are as follows:

    1. 0xFFFFFFF5
    2. 0xFFFFFFE5
    3. 0x00000007
    4. 0xFFFFFEFB

    6)  The answers are as follows:

    1. -5
    2. -22
    3. -13
    4. -8

    7)  \(0.5_{10}\) is represented as \(0.1_2\)

    8)  The answers are as follows:

    1. -12.25
    2. +12.25
    3. -6.5
    4. -7.5

    9)  The answers are as follows:

    1. 0x41340000
    2. 0xC1890000
    3. 0x41AF0000
    4. 0xBF400000

    10)  The answers are as follows:

    1. 0x41
    2. 0x61
    3. 0x30
    4. 0x38
    5. 0x09

    11)  The answers are as follows:

    1. “World” = 0x57 0x6F 0x72 0x6C 0x64
    2. “123” = 0x31 0x32 0x33
    3. “Yes!?” = 0x59 0x65 0x73 0x21 0x 3F

    24.4 Quiz Question Answers, Chapter 4

    1)  yasm

    2)  With the ; (semicolon).

    3)  Section data.

    4)  Section bss.

    5)  Section text.

    6)  The answers are as follows:

    1. bNum db 10

    2. wNum dw 10291

    3. dwNum dd 2126010

    4. qwNum dq 10000000000

    7)  The answers are as follows:

    1. bArr resb 100

    2. wArr resw 3000

    3. dwArr resd 200

    4. qArr resq 5000

    8)  The declarations are:

    global _start

    _start:

    24.5 Quiz Question Answers, Chapter 5

    1)  The relationship is 1:1 (one to one).

    2)  Creation of symbol table, macro expansion, and evaluation of constant expressions.

    3)  Final generation of code, create list file if requested, create object file.

    4)  Combine one or more object files into a single executable, update all relocatable addresses, search user and system libraries, create cross reference file if requested, and create final executable file.

    5)  Attempt to open executable file (verifying existence and permissions), read header information, ask operating system to create new process, if successful, read rest of executable file and load into memory (where specified by operating system), and inform operating system when load is completed. Note, the loader does not run the process.

    6)  Examples might include:

    1. BUFFSIZE + 1
    2. MAX + OFFSET

    Note, assumes that upper case implies defined constant. Many examples possible.

    7)  See Section 5.1, Illustration 4, Overview: Assemble, Link, Load.

    8)  Atrun-time.

    9)  The symbol name and the symbol address.

    24.6 Quiz Question Answers, Chapter 6

    1)  By typing: ddd <progName>

    2)  The“-g”option.

    3)  Executes the program, always starting from the beginning.

    4)  The continue command continues to the next breakpoint.

    5)  Via the menu option Status → Registers.

    6)  The first is the register name, the second is the hex representation of the value, and the third is the decimal representation of the value (excluding some registers such as rip and rsp which are always shown in hex).

    7)  There are multiple ways to exit the debugger including typing exit in the command window, clicking the x (upper left corner), or using the menu options File → Exit.

    8)  There are multiple ways to set a breakpoint including double-clicking on the line, typing b <lineNumber>, or typing b <labelName> (if a label exists on the desired line).

    9)  The debugger command to read commands from a file is; source <fileName>.

    10)  The green arrow points to the next instruction to be executed.

    11)  The answers are as follows:

    1. x/db &bVar1

    2. x/dh &wVar1

    3. x/dw &dVar1

    1. x/dg &qVar1

    2. x/30db &bArr1

    3. x/50dh &wArr1

    4. x/75dw &dArr1

    12) The answers are as follows:

    1. x/xb &bVar1

    2. x/xh &wVar1

    3. x/xw &dVar1

    4. x/xg &qVar1

    5. x/30xb &bArr1

    6. x/50xh &wArr1

    7. x/75xw &dArr1

    13) The command is: x/ug $rsp

    14) The command is: x/5ug $rsp

    24.7 Quiz Question Answers, Chapter 7

    1) The answers are as follows:

    1. Legal

    2. Legal

    3. Illegal, 354 does not fit into a byte

    4. Legal

    5. Illegal, sizes do not match

    6. Illegal, cannot change the value 54

    7. Legal

    8. Legal, while legal it would probably result in an incorrect value

    9. Legal

    10. Legal

    11. Legal, while legal it would probably result in an incorrect value

    12. Illegal, cannot move memory to memory

    13. Illegal, cannot move memory to memory

    14. Legal

    15. Illegal, r16 is not a valid register

    16. Legal

    2)  The answers are as follows:

    1. Copies the byte value at bVar1 into the rsi register treating as an unsigned value thus setting the upper 56 bits to 0.

    2. Copies the byte value at bVar1 into the rsi register treating as a signed value, thus sign extending the upper 56-bits (1's for negative, 0's for positive).

    3)  The answers are as follows:

    1. mov ah, 0

    2. cbw

    4)  The answers are as follows:

    1. movzx eax, ax

    2. cwde

    5)  The answers are as follows:

    1. mov dx, 0

    2. cwd

    6)  The cwd instruction only converts the signed value in ax into a sign value in dx:ax (and nothing else). The movsx instruction copies the word source operand into the double-word destination operand.

    7)  On the first instruction, the destination operand size must be explicitly specified since the source operand, an immediate value of 1, does not have an inherent size associated with it. On the second instruction, the destination operand size can be determined from the source operand (since the eax register is a double- word in this case).

    8)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0000 0000 0009

    2. rbx = 0x0000 0000 0000 000B

    9)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0000 0000 0007

    2. rbx = 0x0000 0000 0000 0002

    10)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0000 0000 0009

    2. rbx = 0xFFFF FFFF FFFF FFF9

    11)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0000 0000 000C

    2. rdx = 0x0000 0000 0000 0000

    12)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0000 0000 0001

    2. rdx = 0x0000 0000 0000 0002

    13)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0000 0000 0002

    2. rdx = 0x0000 0000 0000 0003

    14)  The answers are as follows:

    1. The destination operand cannot be an immediate value (42).

    2. An immediate operand is not allowed since the size/type cannot be determined.

    3. The mov instruction does not allow a memory to memory operation.

    4. An address requires 64-bits which will not fit into the ax register.

    15)  The idiv instruction will divide by edx:eax and edx was not set.

    16)  The operands for the divide a signed (-500), but an unsigned divide is used.

    17)  The word divide used will place the result in the dx:ax registers, but the eax register is used to obtain the result.

    18) The three-operand multiply instructions are only allowed for a limited set of signed multiplication operations.

    24.8 Quiz Question Answers, Chapter 8

    1)  The first instruction places the value from qVar1 into the rdx register. The second instruction places the address of qVar1 into the rdx register.

    2)  The answers are as follows:

    1. Immediate

    2. Memory

    3. Immediate

    4. Illegal, destination operand cannot be an immediate value

    5. Register

    6. Memory

    7. Memory

    8. Illegal, source and destination operands not the same size.

    3)  The answers are as follows (grouped in sets of 4 for clarity):

    1. eax = 0x0000 000A

    4)  The answers are as follows (grouped in sets of 4 for clarity):

    1. eax = 0x0000 0003

    2. edx = 0x0000 0002

    5)  The answers are as follows (grouped in sets of 4 for clarity):

    1. eax = 0x0000 0009

    2. ebx = 0x0000 0002

    3. rcx = 0x0000 0000 0000 0000

    4. rsi = 0x0000 0000 0000 000C

    6)  The answers are as follows (grouped in sets of 4 for clarity):

    1. rax = 0x0000 0010

    2. rcx = 0x0000 0000 0000 0000

    1. edx = 0x0000 0000

    2. rsi = 0x0000 0000 0000 0004

    7)  The answers are as follows (grouped in sets of 4 for clarity):

    1. eax = 0x0000 0002

    2. rcx = 0x0000 0000 0000 0000

    3. edx = 0x0000 0005

    4. rsi = 0x0000 0000 0000 0003

    8)  The answers are as follows (grouped in sets of 4 for clarity):

    1. eax = 0x0000 0018
    2. edx = 0x0000 0000
    3. rcx = 0x0000 0000 0000 0000
    4. rsi = 0x0000 0000 0000 0005

    Quiz Question Answers, Chapter 9

    1)  Therspregister.

    2)  First, rsp = rsp - 8 and then rax register is copied to [rsp] (in that order).

    3)  8 bytes.

    4)  The answers are as follows (grouped in sets of 4 for clarity):

    1. r10 = 0x0000 0000 0000 0003

    2. r11 = 0x0000 0000 0000 0002

    3. r12 = 0x0000 0000 0000 0001

    5)  The array is reversed in memory.

    6)  Memory is used more efficiently.

    24.10 Quiz Question Answers, Chapter 10

    1)  An unambiguous, ordered sequence of steps involved in solving a problem.

    2)  The answer is as follows:

    1. Understand the Problem
    2. Create the Algorithm
    3. Implement the Program
    4. Test/Debug the Program

    3)  No, the steps are applicable to any language or complex problem (even beyond programming).

    4)  An assemble-time error.

    5)  An assemble-time error.

    6)  An assemble-time error.

    7)  A run-time error.

    24.11 Quiz Question Answers, Chapter 11

    1)  At the top (above the data, BSS, and text sections).

    2)  Once for each time the macro is invoked.

    3)  The %% will ensure that a unique label name is generated each time the macrois used.

    4)  If the %% is omitted on a label, the label will be copied, asis, and thus appear to be duplicated.

    5)  Yes. This might be used to exit a macro to an error handling code block (not within the macro).

    6)  The macro argument substitution occurs at assemble-time.

    24.12 Quiz Question Answers, Chapter 12

    1)  Linkage and Argument Transmission.

    2)  The call and the ret instructions.

    3)  Call-by-value.

    4)  Call-by-reference.

    5)  Once, regardless of how many times it is called.

    6)  The current rip is placed on the stack and the rip is changed to the address of called function.

    7)  Save and restore the contents of the callee preserved registers.

    8)  In: rdi, rsi, rdx, rcx, r8, and r9.

    9)  In: edi, esi, edx, ecx, r8d, and r9d.

    10)  That a function may change the value in the register without needing to save and restore it.

    11)  Two of: rax, rcx, rdx, rsi, rdi, r8, r9, r10, and r11.

    12)  Call frame, function call frame, or activation record.

    13)  A leaf function does not call other functions.

    14)  Clear the passed arguments off the stack.

    15)  Twenty-four (24) since three arguments at 8 bytes each (8 x 3).

    16)  The offset is [rbp+16] regardless of which saved registers are pushed.

    17)  Available memory.

    18)  Call-by-reference.

    19)  The 7th argument is at [rbp+16] and the 8th argument is at [rbp+24].

    20)  Memory efficiency since stack dynamic local variables only use memory when needed (when the function is being executed).

    24.13 Quiz Question Answers, Chapter 13

    1)  The rax register.

    2)  The operating system.

    3)  The call code is SYS_write (1). The \(1^{st}\) argument in rdi is the output location STDOUT, the \(2^{nd}\) argument in rsi is the starting address of the characters to output, and the \(3^{rd}\) argument in rdx is the number of characters to write.

    4)  It is unknown how many characters will be entered.

    5)  The rax register will contain the file descriptor.

    6)  The rax register will contain an error code.

    7)  In: rdi, rsi, rdx, r10, r8, and r9.

    24.14 Quiz Question Answers, Chapter 14

    1) The statement is: extern func1, func2

    2)  The statement is: extern func1, func2

    3)  The assembler will generate an error.

    4)  Link-time.

    5)  The linker will generate an unsatisfied external reference error.

    6)  Yes. However, in the debugger, the code would not be displayed.

    24.15 Quiz Question Answers, Chapter 15

    1)  The buffer overflow exploit is typically called stack smashing.

    2)  The C function does not check the array bounds of the input arguments.

    3)  Yes.

    4)  Typing a very large number of characters when input is requested and, if the program crashes.

    5)  A series of nop instructions designed to make the target of a buffer overflow exploit easier to hit.

    6)  Many possible answers. Delete a file, open a network connection, kill a process, etc.

    7)  Use of canaries, implementation of Data Execution Prevention (DEP), and use of Data Address Space Layout Randomization.

    24.16 Quiz Question Answers, Chapter 16

    1)  The operating system. Specifically, the loader.

    2)  The program being executed.

    3)  The name of the executable file.

    4)  The argc refers to argument count and argv refers to the argument vector (starting address of the table of addresses for the string representing each argument).

    5)  In the rdi register.

    6)  In the rsi register.

    7)  The spaces are removed by the operating system so the program does not have to do anything.

    8) No. The program is required to check and determine if that is an error.

    24.17 Quiz Question Answers, Chapter 17

    1)  The end of line character for Linux is linefeed (LF) and the end of line character for Windows is carriage return, line feed (CR, LF).

    2)  Store a subset of the information for quick access.

    3)  They are in the language I/O library functions (i.e., cout, cin, etc.).

    4)  Simplify the programming.

    5)  I/O performance improvement.

    6)  The system service functions require a specific number of characters to read which is not known ahead of time for “one line” of text.

    7)  Keeps a subset of the information at the next higher level in the hierarchy (which is faster than the next lower level).

    8)  Reduces the overhead associated bus contention and memory latency for excessive system reads.

    9)  The variable values must be retained between function calls.

    10)  The end of file must be inferred from the number of characters actually read.

    11)  Many reasons possible, including file being deleted in another Window after the open or the drive (USB) being removed after the open.

    12)  The actual number of characters read will be 0 which must be checked explicitly.

    13)  To ensure the passed line buffer array is not overwritten.

    14)  By initializing the variables to indicate that all buffer characters have been read.

    24.18 Quiz Question Answers, Chapter 18

    1)  The registers are: xmm0, xmm1, xmm2, . . ., xmm15.

    2)  Single precision is 32-bit and double precision is 64-bits.

    3)  Cumulative rounding error associated with the inexact representation of 0.1 in binary.

    4)  Float functions return the value in xmm0.

    5)  None of the floating-point registers are preserved.

    24.19 Quiz Question Answers, Chapter 19

    1)  Concurrency implies multiple different (not necessarily related) processes simultaneously making progress. Parallel processing implies that processes are executing simultaneously.

    2)  Distributed computing and multiprocessing.

    3)  On different computers connected via a network.

    4)  Many possible answers, including Folding@Home and SETI@Home. An Internet search can provide a more complete listing.

    5)  On different cores in the CPU.

    6)  Distributed computing allows a very large number of compute nodes but requires communications over a network which has inherent communication delays.

    7)  Multiprocessing allows very fast communications between processes via shared memory but supports only a limited amount of simultaneous executing threads related to the number of cores available.

    8)  Multiple threads simultaneously writing to a shared variable with no control or coordination.

    9)  No. No problem exists since the variable is not being changed.

    10) Yes. Since the variable is being changed, one thread may alter the value after the other has obtained the value.

    24.20 Quiz Question Answers, Chapter 20

    1)  The operating system is responsible for managing the resources. The resources include CPU cores, primary memory, secondary storage, display screen, keyboard, and mouse.

    2)  An event that alters the sequence of instructions executed by a processor.

    3)  An interrupt that is caused by the current process and needs attention of the kernel.

    4)  An ISR is an Interrupt Service Routine which is executed when an interrupt occurs to service (perform required actions) that interrupt.

    5)  Interrupt Descriptor Table (IDT) which contains the addresses of the Interrupt Service Routines (ISRs) and the gate information.

    6) The interrupt number is multiplied by 16.

    7) The ret instruction will pop the return address from the stack and place it in the rip register. The iret instruction will pop the return address and the preserved flag register contents from the stack and place it in the rip register and rFlag registers.

    8)  The call requires the target address. Since the ISR addresses may change due to hardware changes or software updates, the interrupt mechanism performs a run- time look up for the ISR address.

    9)  That the interrupt timing, when or even if the interrupt might occur, cannot be predicted in the context of the executing code.

    10)  That the interrupt timing can be predicted in the context of the executing code. This is typical of system service calls or exceptions such as division by 0.

    11)  Each instruction changes the rFlag register. After the interrupt is completed, the flag register must be restored to its original value to ensure that the interrupted process is able to resume.

    12) Many possible answers, including I/O devices such as keyboard and mouse, network adapter, secondary storage devices, or other peripherals.

    13) Many possible answers, including dividing by 0.

    14) A maskable interrupt may be ignored briefly where a non-maskable interrupt must be handled immediately.

     

    21.4: Appendix D - Quiz Question Answers is shared under a not declared license and was authored, remixed, and/or curated by LibreTexts.

    1. Back to top
    • Was this article helpful?

    Recommended articles

    1. Article type
      Section or Page
      Autonumber Section Headings
      title with colon delimiters
    2. Tags
      This page has no tags.