7.1: Speed and power in CMOS circuits

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As you should remember from 6.002, the archetype CMOS circuit is shown in Figure 7.2.1. It is composed of two complementary FETs: the upper MOSFET is off for a high voltage input, and the lower MOSFET is off given a low input. The circuit is an inverter.

Screenshot 2021-05-27 at 14.03.21.png — Figure \(\PageIndex{1}\): A CMOS inverter consists of two complementary MOSFETs in series.

For constant voltage input, the circuit has two stable states, as shown in Figure 7.2.2. Because one of the transistors is always off in steady state, the circuit ideally has no static power dissipation.

Screenshot 2021-05-27 at 14.04.57.png — Figure \(\PageIndex{2}\): The two steady state configurations of the inverter. No power is dissipated in either.

But when the input voltage switches the circuit briefly dissipates power. This is known as the dynamic power. We model the dynamics of a CMOS circuit as shown in Figure 7.2.3. In this archetype CMOS circuit one inverter is used to drive more CMOS gates. To turn subsequent gates on an off the inverter must charge and discharge gate capacitors. Thus, we model the output load of the first inverter by a capacitor.

Screenshot 2021-05-27 at 14.05.54.png — Figure \(\PageIndex{3}\): Cascaded CMOS inverters. The first inverter drives the gate capacitors of the second inverter. To examine the switching dynamics of the first inverter, we model the second inverter by a capacitor.

We now consider the key performance characteristics of CMOS electronics.

The Power-Delay Product (PDP)

The power-delay product measures the energy dissipated in a CMOS circuit per switching operation. Since the energy per switching event is fixed, the PDP describes a fundamental tradeoff between speed and power dissipation – if we operate at high speeds, we will dissipate a lot of power.

Imagine an input transition from high to low to the inverter of Figure 7.2.1

Screenshot 2021-05-27 at 14.08.52.png — Figure \(\PageIndex{4}\): Changes in the input voltage cause the output capacitor to charge or discharge dissipating power in the inverter.

If the output capacitor is initially uncharged, the energy dissipated in the PMOS FET is given by:

\[ W = \int^{\tau/2}_{0} dt(V_{DD}-V_{OUT})I \nonumber \]

The current into the capacitor is given by:

\[ I = C\frac{dV_{OUT}}{dt}, \nonumber \]

Combining these expressions:

\[ W = \int^{\tau/2}_{0} dt(V_{DD}-V_{OUT})\frac{dV_{OUT}}{dt} = C\int^{V_{DD}}_{0} dV_{OUT}(V_{DD}-V_{OUT}) = \frac{1}{2}CV_{DD}^{2} . \nonumber \]

Similarly, in the second half of the cycle, when the capacitor is discharged through the NMOS FET, it is straightforward to show that again \(W = \frac{1}{2}CV_{DD}^{2}\). Thus, the energy dissipated per cycle is:

\[ PDP = CV_{DD}^{2} . \nonumber \]