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- https://eng.libretexts.org/Under_Construction/Book%3A_Discrete_Structures/09%3A_Finite-State_Automata/9.03%3A_Finite-State_Machine_States/9.3.01%3A_FSM_StatesThis short video explains more about states in a finite-state machine.
- https://eng.libretexts.org/Bookshelves/Computer_Science/Applied_Programming/Think_Complexity%3A_Exploring_Complexity_Science_with_Python_(Downey)/05%3A_Cellular_Automatons/5.02%3A_Wolframs_experimentIn these experiments, the cells have two states, denoted 0 and 1 or “off" and “on". A rule can be summarized by a table that maps from the state of the neighborhood (a tuple of three states) to the ne...In these experiments, the cells have two states, denoted 0 and 1 or “off" and “on". A rule can be summarized by a table that maps from the state of the neighborhood (a tuple of three states) to the next state of the center cell. The first row shows the state of the system during the first time step; it starts with one cell “on” and the rest “off”. The second row shows the state of the system during the next time step, and so on.
- https://eng.libretexts.org/Bookshelves/Computer_Science/Applied_Programming/Think_Complexity%3A_Exploring_Complexity_Science_with_Python_(Downey)/05%3A_Cellular_Automatons/5.01%3A_A_simple_CAThe state of the cell during time step i is an integer, x i . As an initial condition, suppose x 0 = 0. Arbitrarily, I’ll pick x i+1 = x i + 1, which says that during each time step, the state of the ...The state of the cell during time step i is an integer, x i . As an initial condition, suppose x 0 = 0. Arbitrarily, I’ll pick x i+1 = x i + 1, which says that during each time step, the state of the CA gets incremented by 1. For a 2-state CA, we could write a rule like x i+1 = (x i + 1) % 2, where % is the remainder (or modulus) operator. In the rest of this chapter, we explore one-dimensional (1-D) CAs; in the next chapter we explore two-dimensional CAs.
- https://eng.libretexts.org/Bookshelves/Electrical_Engineering/Electronics/Book%3A_Digital_Circuit_Projects_-_An_Overview_of_Digital_Circuits_Through_Implementing_Integrated_Circuits_(Kahn)/09%3A_Memory_Basics_-_Flip-Flops_and_Latches/9.02%3A_Background_MaterialHence the operation can be thought of as a state transition where the initial state of the computer (S 0 , the two memory values) are added in a black block (combination logic implementing an adder), ...Hence the operation can be thought of as a state transition where the initial state of the computer (S 0 , the two memory values) are added in a black block (combination logic implementing an adder), and the result is a new state (S 1 , with the value of a memory location changed). The second important memory concept is the difference between the static and dynamic memory 8 . Dynamic memory, called DRAM, is implemented using a capacitor and a transistor, and so is simple and cheap.
- https://eng.libretexts.org/Bookshelves/Electrical_Engineering/Electronics/Book%3A_Digital_Circuit_Projects_-_An_Overview_of_Digital_Circuits_Through_Implementing_Integrated_Circuits_(Kahn)/09%3A_Memory_Basics_-_Flip-Flops_and_Latches/9.05%3A_ConclusionSimple circuits can calculate results based on inputs, but to compute a useful result a circuit must be able to maintain a state. SRAM maintains its state so long as current is supplied to the circuit...Simple circuits can calculate results based on inputs, but to compute a useful result a circuit must be able to maintain a state. SRAM maintains its state so long as current is supplied to the circuit, and does not require a refresh cycle, making it faster than DRAM. The problem with using a latch in a circuit, that it requires two latches to be effective, was illustrated. The D flip-flop was then introduced to solve the problem with a D latch.
- https://eng.libretexts.org/Under_Construction/Book%3A_Discrete_Structures/09%3A_Finite-State_Automata/9.01%3A_Introduction/9.1.01%3A_Finite-State_Machine_OverviewRead this article for a quick look at finite state machines.
- https://eng.libretexts.org/Bookshelves/Electrical_Engineering/Electronics/Book%3A_Digital_Circuit_Projects_-_An_Overview_of_Digital_Circuits_Through_Implementing_Integrated_Circuits_(Kahn)/09%3A_Memory_Basics_-_Flip-Flops_and_Latches/9.03%3A_LatchesSo once the circuit is set, so that the outputs are Q and Q', it is easy to see that the output of the top NAND gate is Q (e.g. (Q'*1)' = Q), and the output of the bottom NAND gate is Q' (e.g. (Q*1)' ...So once the circuit is set, so that the outputs are Q and Q', it is easy to see that the output of the top NAND gate is Q (e.g. (Q'*1)' = Q), and the output of the bottom NAND gate is Q' (e.g. (Q*1)' = Q'). So long as the time needed for the circuit to settle is less than the clock speed (the length of the clock pulse), the circuit will become stable with Q = D and Q'=D'. So the result of the clock being high is that the latch will store in its state the value of Q = D and Q' = D'.
- https://eng.libretexts.org/Bookshelves/Computer_Science/Applied_Programming/Think_Complexity%3A_Exploring_Complexity_Science_with_Python_(Downey)/08%3A_Self-organized_criticality/8.02%3A_Sand_PilesThe sand pile model is a 2-D cellular automaton where the state of each cell represents the slope of a part of a sand pile. If so, it “topples” and transfers sand to four neighboring cells; that is, t...The sand pile model is a 2-D cellular automaton where the state of each cell represents the slope of a part of a sand pile. If so, it “topples” and transfers sand to four neighboring cells; that is, the slope of the cell is decreased by 4, and each of the neighbors is increased by 1. For each perturbation, they measure T, the number of time steps the pile takes to stabilize, and S, the total number of cells that topple 1 .
