5.3: Adding the MLA instruction to the MSCPU

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The main advantage of the MSCPU architecture is that it allows new and more complex/powerful operations in hardware. Consider a very common case where a program wants to calculate an element address (ea) for an element in the array. Knowing the Base Address (ba) of the array, the size of each element (size), and the index number (idx), the following formula will calculate the array address for that element.

    ea = ba + (size * idx)

The MSCPU has put the multiply unit in front of the ALU. Over two cycles it runs the multiplication operation (cycle 1) and addition operation (cycle 2). Thus, in one instruction the CPU can calculate the ea using the Multiply and Accumulate (mla) instruction. For example, if ba = 20, size = 4, and the index = 3, the address of array element 3 can be calculated by the following code fragment.

    MOV r1, #20
    MOV r2, #4
    MOV r3, #3
    MLA r0, r2, r3, r1  // The element address (ea) is in r0

This MLA instruction tells the CPU to multiply r2 * r3, add the result to r1, and then store the result in r0. This will be done in two cycles. The first cycle multiplies Rs * Rm and passes the value on to a multiplexer, which selects the multiply unit result to forward to the ALU.

Screen Shot 2022-03-24 at 3.25.56 PM.png

Figure 27: MSCPU MLA operation - Step 1

In the second step, the value register, Rn, is placed on the A bus. The value of the register Rn and the result of the multiplication are passed to the ALU, which adds the values, and passes the result back to the Register Bank to be stored in register Rd.

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Figure 28: MSCPU MLA operation - Step 2

Since this instruction requires two operation units, the multiplier and the ALU, this instruction requires 2 cycles, or has a CPI=2.

The format for the MLA instruction is:

    MLA Rd, Rm, Rs, Rn

An example of using the mla instruction is the same as given above.

    MLA r0, r2, r3, r1