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19.2: Output Circuitry

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  • Figure \(\PageIndex{1}\) presents a further simplification focusing solely on the output portion.

    Output circuitry simplified (from Atmel 2014).
    Figure \(\PageIndex{1}\): Output circuitry simplified (from Atmel 2014).

    First off, the PUD (Pull Up Disable), SLEEP and CLK (CLocK) control lines are common to all bits and ports. We may ignore them for our purposes. The lowest section is removed because it is involved with input functionality. The same goes for the upper section surrounding the MOSFET. Finally, a series of two gates, an inverter and a multiplexer clustered around the middle section have been removed. These serve a particular (and perhaps somewhat esoteric) function, namely the ability to rapidly toggle a bit. Again, this section is not needed for typical functioning.

    Upon simplification we are left with a circuit that centers around two D flip-flops and a few tri-state buffers. The primary signals of interest are WDx and WRx which feed the DDxn and PORTxn flip-flops. DDxn is the Data Direction bit. It determines whether the physical pin is configured for output (writing) or input (reading). PORTxn presents the data that needs to be written. Note that the “x” refers to the port letter, as in Port B, while the “n” refers to the bit number within that port. Thus, the physical pin for bit number two in Port B would be denoted here as PB2 (or alternately, PORTB.2). The collection of all eight bits of DDxn is referred to as the Data Direction Register, or DDR. The Data Direction Register for Port B would be referred to as DDRB. Each port will have these registers mapped in memory. That is, for Port B there will be a DDRB for direction control and a PORTB for writing data (there is also a PINB for reading, more on that later). Similarly there will a DDRC and PORTC (and PINC) for Port C, and so on for as many ports as the controller has (B, C and D for the ATmega 328P).

    To understand how the circuit works, recall that a D flip-flop’s Q output simply echoes the logic level present at the D input when the control signal transitions from low to high (i.e., positive edge trigger). Note that the output of PORTxn feeds a tri-state buffer which in turn feeds the physical pin. In order to write data to the pin, a logic high is first placed on the data bus. The WDx signal is pulsed which transfers the logic high to Q of DDxn. This high level enables the tri-state buffer connected to Pxn. The port bit is now configured for output and it will stay in this mode until WDx is re-asserted. The desired data (high or low bit) is now placed on the data bus. The WRx signal is pulsed which transfers the logic level to Q of PORTxn. This feeds the afore-mentioned tri-state which transfers the data bit to the output. This level will remain until WRx is re-asserted. If WDx and WRx are never re-asserted, the output pin level will never change. In order to write new data to the output pin, the desired data bit is placed on the bus and WRx is pulsed. It is not necessary to re-load DDxn and re-assert WDx each time.

    For example, suppose we wish to flash an LED several times. We could do this by attaching an LED to the pin and then toggling the pin from high to low repeatedly. First, we would write a high to DDxn to establish output (write) mode. Then we would write a high to PORTxn, turning on the LED. After a short wait we would write a low to PORTxn, turning off the LED. After a further short wait we would write another high to PORTxn (turning the LED back on) and continue the process in like manner for as many flashes as we need.

    The final two tri-state buffers associated with the RDx and RRx signals allow us to read the current states of the direction and port bits.

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