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3.1: 3-Address Machines

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    The MIPS CPU organization is called a 3-address machine. This is because most operations allow the specification of 3 registers as part of the instruction. To understand this better, consider the following figure, which is similar to figure 2.2 except that now the ALU logic portion of the diagram is emphasized.

    Figure 3-1: MIPS computer architecture

    Screen Shot 2020-06-28 at 11.59.18 PM.png

    Most MIPS operators take 3 registers as parameters, which is the reason it is called a 3-address machine. They are: the first input to the ALU, always Rs (the first source register); the second input to the ALU, either Rt (the second source register) or an immediate value; and the register to write the result to, Rd (the destination register). All operators, with the exception the shift operators, used in this chapter will follow this format. Even the shift operators will appear to follow this convention, and it will be only when encoding them into machine code in Chapter 4 that they will appear different.

    The final thing to note about this diagram is that the ALU takes two inputs. The first is always the Rs register. The second input is determined by the type of operator, of which there will be two types that will be looked at in this chapter. The first type of operator is an Register (R) operator. The register operator will always take the second input to the ALU from the Rt register. The format of all R operators will be as follows:

    [operator] Rd, Rs, Rt

    This syntax means the following:

    Rd <- Rs [operator] Rt

    The second type of operator is an Immediate (I) operator. There are a limited number of operations for which an I operator is defined. When they are defined, the operation they perform will be specified by appending an "i" to the end of the operator name, and the format will replace the Rt parameter in the R operator with the I (immediate) value which comes from the instruction. The format of all I operators is:

    [operator]i Rt, Rs, Immediate value

    This syntax means the following:

    Rt <- Rs [operator]i Immediate value

    This helps explain the difference between a constant and an immediate value. A constant is a value which exists in memory, and must be loaded into a register before it is used. An immediate value is defined as part of the instruction, and so is loaded as part of the instruction. No load of a value from memory to a register is necessary, making the processing of an immediate value faster than processing a constant.

    There are few real (native) operators in MIPS do not follow this 3-address format. The Jump (J) operator is the most obvious, but the branch operators and the store operators are also anomalous in that they drop the Rd operator. These will be covered later and the text, and the reason for the format will be obvious.

    Other operations in MIPS will appear to not follow these formats. However these operations are pseudo operations, and do not exist in the real MIPS instruction set. Some of these pseudo operations, such as move and li, have already been seen in chapter 2. These operators do not require 3 addresses, but they are translated into real operations which do. This will be covered in this chapter.

    This page titled 3.1: 3-Address Machines is shared under a CC BY 4.0 license and was authored, remixed, and/or curated by Charles W. Kann III.

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