4.1: Instruction Set Architecture (ISA)

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When implementing a CPU, a virtual representation must first be created to specify a number of architectural decisions that must be made. Obvious things such as:

Will the CPU be a Complex Instruction Set CPU (CISC) or a Reduced Instruction Set CPU (RISC)?
What are the supported data types, for example will the CPU support ints, shorts, characters, floats, doubles, etc?
How big to make the data items, such as integers and addresses. Often this is related to and called the word size for a CPU.
The format of data items, such as using two’s complement for integer values, IEEE 754 format for floats, and ASCII for characters. The format for all supported data types must be specified.
How many registers will exist and how they will be used.
How is data transferred between units in the CPU, called the processor datapath.
How will data be provided to the ALU, or more specifically will the computer be a 0- address (stack), 1-address (accumulator) or 2/3-address (general register) organization.
When designing a CPU, memory can be accessed directly by instructions, or the access to memory can be limited to load and store instructions. The ARM CPU falls into the latter category of a load and store architecture.

9. Is there a unified memory, called a Von Neumann or Princeton architecture, or is the memory divided between text and data segments, called a Harvard architecture.

This section will address specifically the last three issues: the type of datapath for the data, how memory is accessed, and the memory organization.

The ARM architecture is a modified version of a 3-address, load and store architecture. Therefore, the rest of this chapter will be cover a generic version of 3-address load and store architecture that is capable of running ARM instructions.