4: 3-address instruction set

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At its core the ARM instruction is a 3-address load and store CPU. Because the assembly language is built to support the underlying architecture, the ARM assembly instruction set is also based on 3-address load and store instructions. A 3-address CPU says that the instructions will have an operator and 3 operands (a destination register and two source values). The source values can be either two registers, or a register and a number. So, instructions in this chapter will be of the format:

    Operator r1, r2, r3

    Operator r1, r2, #number

Many programs can be implemented using only a 3-address instruction subset of the ARM instructions. This chapter will present the ARM instructions as 3-address instructions. Note that this will be done using completely valid ARM instructions, no fake or pseudo instructions will be covered. The instruction set will be developed by restricting the inputs to some operations.

To actually understand the ARM CPU, a model closer to a real ARM CPU will be developed in Chapter 5, the MSCPU. This CPU will be modified to extend the instructions in this chapter. It will also clarify some questions that may arise from having simplified the architecture. For example, when documenting the instructions in this chapter the use of registers will appear arbitrary. When to use Rn verses Rs will appear to be arbitrary, and Rm will sometimes be the second register in the instruction, and other times the third register in the instruction. The order of the registers and immediate values will be inconsistent. The instructions in this chapter will work as documented, but the reasons for the differences will be explained in Chapter 6.