# 8.2: Circuit Diagram for a MUX

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The truth table in Figure 8.1.2 characterizes a 4-to-1 MUX.

Using this truth table, the 4-to-1 MUX can be built using by realizing I0 is only selected when S1S0 are 00, I1 is only selected with S1S0 are 01, etc. So the I0 bit can be sent to an AND gate with the result of the inverted value of S1 and S0. This AND gate will always be 0 except when S1S0 are 00, when it will be I0. In this manner I1, I2, and I3 can be selected by an AND operation with 01, 10, and 11 respectively.

Note that only one input value can ever be selected for any value of S0S1. The one input which is sent to an AND gate with 1 will be 0 or 1, based on its input. The result of all of the AND gates are sent to a 4-way OR gate. Remembering 0 + X is always X, the result of the OR gate will represent the one input selected. It can be 0 or 1, but it will be 0 or 1 based on the value of the selected input.

The schematic of a MUX is given in the Figure $$\PageIndex{1}$$.

An interesting thing about this circuit is that a decoder is implemented as part of the multiplexer circuit, as shown in the outlined part of Figure $$\PageIndex{1}$$. This suggests another way to implement the MUX using a decoder to select which input line to select. This is shown in Figure $$\PageIndex{2}$$. We will make use of this in designing our implementation of a MUX.

This page titled 8.2: Circuit Diagram for a MUX is shared under a CC BY 4.0 license and was authored, remixed, and/or curated by Charles W. Kann III via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.