5.12: Ballistic Quantum Wire FET Current-Voltage Characteristics at T = 0K.

The electrostatic capacitances are shown in Figure 5.11.2 using the quantum dot model of the quantum wire. In this example we ignore source and drain capacitances. The gate capacitor was defined in Figure 5.10.1 as \(C_{G} = \text{1 aF per nanometer of gate length}\).

We compare quantum and electrostatic capacitances in Figure 5.12.1, we find that the single mode wire has relatively few states, hence its quantum capacitance is small, and above the band edge it operates in the zero charging/insulator regime; even in the ON state charging effects are negligible and we can take \(U = -qV_{GS}\).

Figure \(\PageIndex{1}\): A comparison between the electrostatic and quantum capacitances shows that that \(C_{Q} \gg C_{ES}\) only at the conduction band edge. But as the channel fills with charge, the wire returns to the insulator regime.

In forward bias (when the drain potential is lower than the source), there are three regimes of operation:

OFF: \(V_{GS} < V_{T}\)

Let‟s define the threshold voltage as the potential difference between the source and the conduction band minimum. Thus, in this example, \(V_{T} = 0.3 V\). Recall that the gate potential is relative to the source potential. So when \(V_{GS} < V_{T}\), electrons cannot be injected from the source. Hence no current can flow for positive drain voltages. This is the OFF state of the FET.

Note that source drain current can flow for \(T > 0K\) since the tail of the Fermi distribution for electrons in the source overlaps with states in the wire. The current follows Equation (5.8.6).

Figure \(\PageIndex{2}\): Energy line up for FET in the OFF state. There are no channel states between the source and drain chemical potentials.

The linear regime: \(V_{GS} > V_{T},\ V_{DS} < V_{GS}-V_{T}\)

This is known as the linear regime because the current scales linearly with the drain source potential. Equation (5.10.6) reduces to

\[ I_{DS} = \frac{2q^{2}}{h} V_{DS} \nonumber \]

Note that the FET exhibits the quantum limit of conduction in this regime. Its transconductance, however, is zero.

Figure \(\PageIndex{3}\): In the linear regime, the current is limited by the source drain potential.

Saturation: \(V_{GS} > V_{T},\ V_{DS} > V_{GS}-V_{T}\)

Once the drain potential exceeds \(V_{GS}-V_{T}\), all the charge in the channel is uncompensated and injected into the drain. Thus, the current is limited by the gate potential. This is known as saturation.

\[ I_{DS} = \frac{2q^{2}}{h} (V_{GS}-V_{T}) \nonumber \]

The transconductance for a single mode wire in saturation is

\[ g_{m} = \frac{2q^{2}}{h} \nonumber \]

Figure \(\PageIndex{4}\): In the saturation regime, the current is limited by the gate source potential.

Figure 5.21.5 plots the forward bias characteristics of the FET both at T = 0K, and room temperature. At room temperature, the characteristics were determined numerically since the transition from linear to saturation regimes is blurred by thermal activation of electrons above the Fermi level.

Figure \(\PageIndex{5}\): Forward bias characteristics for a quantum wire FET at (a) T = 0K, and (b) room temperature.