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Engineering LibreTexts

3.5: MOS Regimes

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Graph of I_d vs V_ds, in the first quadrant. The graph takes the form of a straight line passing through the origin, with a slope equal to the product of mu_s, c_ox, and W divided by L, the whole multiplied by the difference between V_gs and V_T.

Figure 3.5.1: The MOSFET I-V graph in the linear regime

Caution is advised with this result, however, because we have overlooked something quite important. Let's go back to our picture of the gate and the batteries involved in the operation of the MOS transistor. Here we have explicitly shown the channel as a black band and we have introduced a new quantity, Vc(x), the voltage along the channel, and a coordinate x, which tells us where we are on the channel relative to the source and drain. Note that once we apply a drain source potential, Vds, the potential in the channel Vc(x) changes with distance along the channel. At the source end, Vc(0)=0 as the source is grounded. At the drain end, Vc(L)=Vds. We will define a voltage Vgc, which is the potential difference between the gate voltage and the voltage in the channel. Vgc(x)VgsVc(x)

Thus, Vgc goes from Vgs at the source end to VgsVdsat the drain end.

Biased MOSFET transistor with the source on the left and the drain on the right. The voltage of the channel between the source and drain is a function of x, the distance from the left edge of the channel. At x=0, the channel voltage is 0; at x=L, on the right edge of the channel, the channel voltage is V_ds.

Figure 3.5.2: Effect of Vds on channel potential

The net charge density in the channel depends upon the potential difference between the gate and the channel at each point along the channel, not just VgsVT. Thus we have to modify the equation of another module to take this into account. Qchan=cox(Vgc(x)VT)=cox(VgsVc(x)VT)

This, in turn, modifies the integral relation between Id and Vgs. Vds0μscox(VgsVTVc(x))W dVc(x)=L0Id dx

Equation 3.5.3 is only slightly harder to integrate than the one before, and we get for the drain current Id=μscoxWL((VgsVT)VdsVds22)

This equation is called the Sah Equation after C.T. Sah, who first described the MOS transistor operation this way back in 1964. It is very important because it describes the basic behavior of the MOS transistor.

Note that for small values of Vds, a previous equation and Equation 3.5.4 will give us the same Id-Vds behavior, because we can ignore the Vds2 term in Equation 3.5.4. This is called the linear regime because we have a straight-line relationship between the drain current and the drain-source voltage. As Vds starts to get larger however, the squared term will begin to kick in and the plot will start to curve over. Obviously, something is causing the current to drop off as Vds gets larger. This is because the voltage difference between the gate and the channel is becoming less, which means there is less charge in the channel to provide conduction. We can graphically show this by making the channel layer look thinner as we move from the source to the drain. Equation 3.5.4, and in fact, Figure 3.5.3 would make us think that if Vds gets large enough, that the drain current Id should actually start decreasing again, and maybe even become negative! This does not seem very intuitive, so let's take a look in more detail at the place where Id becomes a maximum. We can define Vd sat as the source-drain voltage where Id becomes a maximum. We can find this by taking the derivative of Id with respect to Vds and setting the derivative to 0. ddVds(Id)=0=μscoxWL(VgsVTVd sat)

On dropping constants: Vd sat=VgsVT

Rearranging this equation gives us a little more insight into what is going on. VgsVd sat=VT=Vgc(L)

Graph of I_d vs V_ds, in the first quadrant. The curved graph takes the shape of a concave-down parabola starting at the origin, until the maximum of the parabola is reached; for larger values of V_ds, the general form of the parabola continues, but the graph is broken into many short segments.

Figure 3.5.3: I-V characteristics showing turn-over

Perspective view of the rectangular-prism source and drain, located on the left and right respectively. The channel between them is represented as a right triangular prism, with the top face flush with the top faces of the source and drain, the base of the triangle located adjacent to the source, and the triangle's apex is touching the top left corner of the drain.

Figure 3.5.4: Effect of Vds on the channel

At the drain end of the channel, when Vds just equals Vd sat, the difference between the gate voltage and the channel voltage, Vgc(L) is just equal to VT, the threshold voltage. Any further increase in Vds and the difference between the gate and the channel (in the channel region just near the drain) will drop below the threshold voltage. This means that when Vds gets bigger than Vd sat, the channel just near the drain region disappears! We no longer have sufficient voltage between the gate and the channel region to maintain an inversion layer, so we simply revert to a depletion condition. This is called pinch off, as seen in Figure 3.5.5.

Channel in pinch-off: similar to Figure 4 from above, but with the channel not extending all the way to the drain. There is a small gap between the drain and the apex of the right-triangular prism of the channel.

Figure 3.5.5: Channel in pinch-off

What happens to the drain current when we hit pinch off? It looks like it might go to zero, but that is not the right answer! Although there is no active channel in the pinch-off region, there is still silicon — it just happens to be depleted of all free carriers. There is an electric field going from the drain to the channel, and any electrons which move along the channel to the pinch-off region are sucked across by the field, and enter the drain. This is just like the current that flows in the reverse saturation condition of a diode. There are no free carriers in the depletion region of the diode, yet Isat does flow across the junction region.

Under pinch-off conditions, further increases in Vds, does not result in more drain current. You can think of the pinched-off channel as a resistor, with a voltage of Vd sat across it. When Vds gets bigger than Vd sat, the excess voltage appears across the pinch-off region, and the voltage across the channel remains fixed at Vd sat. If the channel keeps the same charge, and has the same voltage across it, then the current through the channel (and into the drain) will remain fixed, at a value we will call Id sat.

There is one other figure which sometimes helps in seeing what is going on. We will plot potential energy for an electron, as it traverses across the channel. Since the source is at zero potential and the drain is at Vds, an electron will loose potential energy as it flows from the source to the drain. Figure 3.5.6 shows some examples for various values of Vds:

Going from source to drain, electron potential energy decreases. The graph takes the form of straight lines with relatively shallow slopes running from 0 to -V_ds1 and -V_ds2; to reach the values of -V_dsat, -V_ds4, and -V_ds5, the graph has shallow slopes for most of the channel's length before sharply transitioning to a steeper slope for the last portion.
Figure 3.5.6: Electron potential energy drop going from source to drain.

For the first two drain voltages, Vds1 and Vds2, we are below pinch-off, and so the voltage drop across Rchannel increases as Rchannel increases, and hence, so does Id. At Vd sat, we have just reached pinch-off, and we are starting to see the "high field" depletion region begin to develop. Since electric field is just the derivative of the potential, the slope of curves in Figure 3.5.6 gives you an idea of how big the electric field will be. For further increases in Vds, such as Vds4 and Vds5 all of the additional voltage just shows up as a high field drop at the end of the channel. The voltage drop across the conducting part of the channel stays fixed (more or less) at Vd sat and so the drain current stays more or less fixed at Id sat. Substituting the expression for Vsat into the expression for Id, we can get an expression for Id sat: Id sat=μscoxW2L(VgsVT)2

We can define a new constant, k, where k=μscoxWL

So that Id sat=k2(VgsVT)2

What this means for Figure 3.5.3 is that when Vds gets to Vd sat, we simply hold Id fixed from then on, with a value of Id sat. For different values of Vg, the gate voltage, we are going to have a different Id-Vds curve, and so once again, we end up with a family of "characteristic curves" for the MOSFET. These are shown in Figure 3.5.8.

Graph of I_d vs V_ds, in the first quadrant.Starting at the origin, the graph rises in a concave-down parabola that smoothly transitions to a horizontal line at the point (V_dsat, I_dsat).

Figure 3.5.7: Complete I-V curve for the MOSFET

Set of characteristic curves for a MOSFET, with each one following the pattern of the curve from Figure 7 above with varying steepness for the initial curves and varying slopes for the later linear portions.

Figure 3.5.8: Characteristic curves for a MOSFET

This also gives us a fairly easy way in which to "sketch" a set of characteristic curves for a given device. Suppose we have a MOS field effect transistor which has a threshold voltage of 2 volts, a width of 10 microns, and a channel length of 1 micron, an oxide thickness of 150 angstroms, and a surface mobility of 400 CVsec. Using εox=3.3×1013 Fcm, we get a value of 2.2×107 FC for cox. This then makes k have a value of k=μscoxWL=4002.2×107101=8.8×104 ampvolt2


This page titled 3.5: MOS Regimes is shared under a CC BY 1.0 license and was authored, remixed, and/or curated by Bill Wilson via source content that was edited to the style and standards of the LibreTexts platform.

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