3: FETs
- Page ID
- 88489
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\(\newcommand{\avec}{\mathbf a}\) \(\newcommand{\bvec}{\mathbf b}\) \(\newcommand{\cvec}{\mathbf c}\) \(\newcommand{\dvec}{\mathbf d}\) \(\newcommand{\dtil}{\widetilde{\mathbf d}}\) \(\newcommand{\evec}{\mathbf e}\) \(\newcommand{\fvec}{\mathbf f}\) \(\newcommand{\nvec}{\mathbf n}\) \(\newcommand{\pvec}{\mathbf p}\) \(\newcommand{\qvec}{\mathbf q}\) \(\newcommand{\svec}{\mathbf s}\) \(\newcommand{\tvec}{\mathbf t}\) \(\newcommand{\uvec}{\mathbf u}\) \(\newcommand{\vvec}{\mathbf v}\) \(\newcommand{\wvec}{\mathbf w}\) \(\newcommand{\xvec}{\mathbf x}\) \(\newcommand{\yvec}{\mathbf y}\) \(\newcommand{\zvec}{\mathbf z}\) \(\newcommand{\rvec}{\mathbf r}\) \(\newcommand{\mvec}{\mathbf m}\) \(\newcommand{\zerovec}{\mathbf 0}\) \(\newcommand{\onevec}{\mathbf 1}\) \(\newcommand{\real}{\mathbb R}\) \(\newcommand{\twovec}[2]{\left[\begin{array}{r}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\ctwovec}[2]{\left[\begin{array}{c}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\threevec}[3]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\cthreevec}[3]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\fourvec}[4]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\cfourvec}[4]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\fivevec}[5]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\cfivevec}[5]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\mattwo}[4]{\left[\begin{array}{rr}#1 \amp #2 \\ #3 \amp #4 \\ \end{array}\right]}\) \(\newcommand{\laspan}[1]{\text{Span}\{#1\}}\) \(\newcommand{\bcal}{\cal B}\) \(\newcommand{\ccal}{\cal C}\) \(\newcommand{\scal}{\cal S}\) \(\newcommand{\wcal}{\cal W}\) \(\newcommand{\ecal}{\cal E}\) \(\newcommand{\coords}[2]{\left\{#1\right\}_{#2}}\) \(\newcommand{\gray}[1]{\color{gray}{#1}}\) \(\newcommand{\lgray}[1]{\color{lightgray}{#1}}\) \(\newcommand{\rank}{\operatorname{rank}}\) \(\newcommand{\row}{\text{Row}}\) \(\newcommand{\col}{\text{Col}}\) \(\renewcommand{\row}{\text{Row}}\) \(\newcommand{\nul}{\text{Nul}}\) \(\newcommand{\var}{\text{Var}}\) \(\newcommand{\corr}{\text{corr}}\) \(\newcommand{\len}[1]{\left|#1\right|}\) \(\newcommand{\bbar}{\overline{\bvec}}\) \(\newcommand{\bhat}{\widehat{\bvec}}\) \(\newcommand{\bperp}{\bvec^\perp}\) \(\newcommand{\xhat}{\widehat{\xvec}}\) \(\newcommand{\vhat}{\widehat{\vvec}}\) \(\newcommand{\uhat}{\widehat{\uvec}}\) \(\newcommand{\what}{\widehat{\wvec}}\) \(\newcommand{\Sighat}{\widehat{\Sigma}}\) \(\newcommand{\lt}{<}\) \(\newcommand{\gt}{>}\) \(\newcommand{\amp}{&}\) \(\definecolor{fillinmathshade}{gray}{0.9}\)- 3.1: Introduction to MOSFETs
- This page details the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), contrasting it with bipolar junction transistors. It describes the structure of a silicon block with p-type and n-type doping, emphasizing the need for an n-type layer for current flow. The page also outlines the creation of a silicon dioxide insulating layer and the deposition of a conductor (gate) using polycrystalline silicon, along with a brief mention of epitaxial layers for specialized uses.
- 3.2: Basic MOS Structure
- This page covers the MOS (Metal-Oxide-Semiconductor) structure, detailing how gate voltages affect a p-type silicon substrate. It explains band diagrams, charge distributions, and the formation of accumulation and depletion regions. The concept of threshold voltage (\(V_{T}\)) is introduced, highlighting that surpassing \(V_{T}\) leads to the creation of an inversion layer of electrons, enabling conduction.
- 3.3: Threshold Voltage
- This page covers the analysis of threshold voltage (\(V_T\)) in field effect transistors, detailing how to determine it through charge distribution and Gauss' Law. It derives expressions for electric fields and voltage drops related to \(V_T\) based on parameters like acceptor density.
- 3.4: MOS Transistor
- This page covers the structure and operation of a MOSFET, explaining its oxide layer, gate structure, and the terms source and drain. It introduces the inversion layer concept and discusses channel resistance. The page derives formulas for surface charge density and drain current \(I_d\), establishing relationships among \(I_d\), \(V_{\text{gs}}\), and \(V_{\text{ds}}\) related to MOS transistor behavior.
- 3.5: MOS Regimes
- This page explains the operation of MOSFET transistors, focusing on the relationship between drain current (\(I_{d}\)) and drain-source voltage (\(V_{\text{ds}}\)), with particular emphasis on how gate voltage (\(V_{\text{gs}}\)) and device dimensions affect \(I_{d}\). It introduces key concepts such as channel potential and the pinch-off phenomenon, detailing the behavior of \(I_{d}\) in the pinch-off region and how it stabilizes at \(I_{\text{d sat}}\).
- 3.6: Plotting MOS I-V
- This page covers the calculation and plotting of \(V_{\text{d sat}}\) and \(I_{\text{d sat}}\) for different \(V_{\text{gs}}\) in a MOSFET, detailing the creation of a value table and the corresponding \(I-V\) graph. It explains measuring parameters \(k\) and \(V_{T}\) in a MOSFET circuit, illustrating how the relationship between \(I_{d}\) and \(V_{ds}\) can yield a linear plot for determining \(V_{T}\) through extrapolation, despite potential non-ideality effects.
- 3.7: Models
- This page explains how to determine the threshold voltage (\(V_{T}\)) of a MOS transistor by examining its characteristics in the linear regime. It models the drain current (\(I_{d}\)) concerning gate voltage (\(V_{\text{gs}}\)) and compares MOSFETs to bipolar transistors, emphasizing advantages like easier manufacturing and suitability for integrated circuits. The content prepares the reader for understanding logic circuits involving these devices.
- 3.8: Inverters and Logic
- This page covers the basic concept of an inverter in digital circuits, detailing its role in outputting the opposite signal of its input. It explains MOSFET operation within the inverter and discusses the load-line equation that governs current and voltage interactions. Performance limits regarding output voltage levels are examined, along with NAND and NOR circuits as essential components for complex logic.
- 3.9: Transistor Loads for Inverters
- This page covers depletion mode MOSFETs, which have a channel at \(V_{g} = 0\) due to impurities that create a negative threshold voltage. It contrasts their operational characteristics with enhancement mode MOSFETs and discusses their application in inverter circuits. Although depletion mode devices offer beneficial transfer characteristics, they still face challenges with current draw in larger circuits, signaling a need for further advancements in MOS technology.
- 3.10: CMOS Logic
- This page covers PMOS transistors and CMOS technology, focusing on their design, function, and contrasts with NMOS transistors. It details the operation of PMOS devices, which utilize p-type sources and drains with n-type substrates, activated by negative gate-source voltages.
- 3.11: JFET
- This page covers the Junction Field Effect Transistor (JFET), detailing its structure of a p-type substrate with n-type regions and its operation through reverse bias to create a depletion region. The gate voltage controls the size of this region to manage drain current. While JFETs are considered less user-friendly compared to MOSFETs due to their depletion-mode characteristics, they provide benefits like lower gate capacitance.
- 3.12: Electrostatic Discharge and Latch-Up
- This page emphasizes the critical need for careful handling of MOS circuits to prevent electrostatic discharge (ESD) damage caused by static charges. It discusses latch-up in CMOS circuits, where unintended current paths can create short circuits between power and ground, often triggered by factors like incorrect output connections. The page highlights the importance of design measures implemented by IC designers to mitigate these risks.