3.10: CMOS Logic

Consider the following, shown in Figure \(\PageIndex{1}\).

Figure \(\PageIndex{1}\): A PMOS transistor

This looks a lot like our previous MOSFET except that now we have an n-type substrate and the source and drain regions are p-type. If we apply a negative \(V_{\text{gs}}\) (with the source connected to the n-type substrate) then the induced negative charge on the gate will drive away the electrons, and if the bands under the gate are bent up sufficiently, form an inversion layer of holes (see Figure \(\PageIndex{2}\), thus making an enhancement mode p-channel MOSFET, or a PMOS transistor. (As opposed to an NMOS transistor which we studied first.). Note that a PMOS transistor will have a negative \(V_{T}\). That is, the gate voltage has to be less than the source/substrate voltage in order to turn the device on. The more negative \(V_{\text{gs}}\) is, the more current we will have flowing through the device.

Figure \(\PageIndex{2}\): Inversion of an n-type layer

It turns out that a combination of both an n-channel and a p-channel device on the same circuit can be very advantageous. Such technology is called CMOS, for "complementary MOS". Here is how we use a p-channel transistor in the inverter circuit.

First of all, however, we have to see how we would make one. There is a fundamental problem in trying to use both n-channel and p-channel devices in the same circuit. What is it? It would seem we need two different kinds of substrates, both a p-type substrate for the n-channel transistor, and an n-type substrate for the p-channel device. There is a way around this problem by making what is called a tank or a moat. A moat is a relatively deep region of one type of material placed into a host substrate of the opposite type (Figure \(\PageIndex{3}\)). We can put n-type source/drain regions into the p-substrate and p-type source/drain regions into the n-moat. In Figure \(\PageIndex{4}\), we will also show the gates, and how the whole inverter is connected together.

Figure \(\PageIndex{3}\): Preparing for a CMOS inverter

Figure \(\PageIndex{4}\): A CMOS inverter

Now let's draw the schematic: A p-channel device is drawn just like an n-channel device, except we put a little "bubble" on the gate to signify that it is a MOSFET of a different color. Although we usually don't do this all the time, we have also shown the substrate connections in this diagram. These connections show that a MOSFET is at least a four-terminal device, not a three-terminal one as people often assume. Since, in a p-channel device, the substrate is n-type, we show the substrate connection as an outward pointing arrow. The p-type substrate for the n-channel device is shown as an inward pointing arrow. The n-channel substrate is connected to ground, and the p-channel substrate is connected to \(V_{\text{dd}}\). Note that since the n-moat is at \(V_{\text{dd}}\) and the p-substrate is at ground, the moat-substrate p-n junction is reverse biased, and so no current should flow between them.

Figure \(\PageIndex{5}\): Schematic of a CMOS inverter

We usually do not label the source and drain either, but we do here, just for completeness. Note that unlike the bipolar transistor, the FET is truly a symmetric device. There is really no way to tell the source from the drain. By convention, we call the element which is connected to the substrate (or moat) the source, and the other the drain. You will sometimes hear the region under the gate (either substrate or moat) referred to as the backbody.

Now let's see how this circuit works. If \(V_{\text{in}}\) is high (at or near \(V_{\text{dd}}\)) the NMOS transistor will be turned on. The voltage between the gate and substrate of the p-channel device is at or near zero. The gate is at \(V_{\text{dd}}\) and so is the moat! Hence the upper transistor will be turned off. The output will thus be low.

If the input voltage is at or near ground (a "low") then the n-channel device is turned off. The voltage between the gate and substrate of the p-channel device is now \(\simeq \left( -V_{\text{dd}} \right)\). (The gate is \(\simeq 0\) and the substrate is at \(V_{\text{dd}}\).) If the PMOS transistor has a threshold voltage \(V_{T}\) of, say, \(-2 \mathrm{~V}\), then it will be turned on and the output will be high. Note however, that in either state, high or low, there is no static current flowing through the inverter.

The transfer characteristics for this circuit are a little more complicated. First, let's make sure we have our voltages and currents defined. From Figure \(\PageIndex{6}\), the n-channel gate-source voltage, \(V_{\text{gs-}n}\), is just \(V_{\text{in}}\). The gate-source voltage for the p-channel device, \(V_{\text{gs-}p}\), is \(V_{\text{in}} - V_{\text{dd}\); \(V_{\text{ds-}p}\), the drain-source voltage for the p-channel transistor can be written as \(V_{\text{ds-}n} - V_{\text{dd}}\). For current, \(I_{d \text{-} n} = I_{d \text{-} p} = I_{d}\). As seen in Figure \(\PageIndex{7}\), we have two sets of characteristic curves. Note that since \(V_{\text{gs-}p} = V_{\text{in}} - V_{\text{dd}}\), when \(V_{\text{in}} = 0 \mathrm{~V}\), \(V_{\text{gs-}p} = -5 \mathrm{~V}\) and so the transistor is strongly turned on.

Figure \(\PageIndex{6}\): Defining voltages

Figure \(\PageIndex{7}\): Drain currents for the two transistors as a function of input voltage and \(V_{\text{ds}}\)

We have a number of different "load lines" in this case, because for each \(V_{\text{in}}\) we have a different curve for both the n- and p-channel transistors. This is shown in Figure \(\PageIndex{8}\). The black spots show the point of intersection. Follow a few of the curves along to see if you agree with where the spots have been placed. We have also added a pair of dotted curves for \(V_{\text{in}} = 2.5 \mathrm{~V}\) so we can get the "turn-over" point. Projecting the location of the black dots to the \(V_{\text{ds-}n}\) (or \(V_{\text{out}}\)) axis will gives us a value for \(V_{\text{out}}\) for each of the input voltages, \(V_{\text{in}}\). The resulting curve is shown in Figure \(\PageIndex{9}\). This gives us a good "feel" for how the inverter works, and how the output varies with the input. Note that this transfer curve is quite symmetric about 2.5 volts, and goes all the way from +5 to 0 volts on the output.

Figure \(\PageIndex{8}\): Getting the transfer function

Figure \(\PageIndex{9}\): CMOS inverter transfer characteristics